Aura Semiconductor Pvt. Ltd

Augusto Marques

Raja Prabhu J

Ankit Seedher

Srinath Sridharan

Sandeep Perdoor

Vaibhav Maheshwari

Nigesh Baladhandapani

Sriharsha Vasadi

Sharanaprasad Melkundi

Kulbhushan Thakur

A frequency divider includes a set of frequency-dividing units coupled in series in a sequential order, with the sequence of frequency-dividing units including a lowest unit and a highest unit, with the remaining units being disposed in series between the lowest unit and the highest unit. The lowest unit is coupled to receive an input clock whose frequency is to be divided and provided as an output clock. Each frequency-dividing unit in the set is coupled to receive a corresponding first clock as an input and is operable to generate a corresponding second clock as an output. The frequency divider includes a logic block to generate a first set of edges of the output clock synchronous with the input clock. The logic block is designed to generate a second set of edges of the output clock synchronous with the output clock of a highest operative frequency-dividing unit in the set.

Avoiding very low duty cycles in a divided clock generated by a frequency divider

A phase locked loop (PLL) includes a multiplexer (MUX), a phase detector, a filter block, an oscillator, a frequency divider, and a clock switch controller, and achieves hitless switching between a primary clock and a redundant clock. The clock switch controller, upon detecting a condition requiring switching from the primary clock to the redundant clock, is operable to restart the feedback divider synchronously with respect to the redundant clock, and derive the output of the PLL from the redundant clock. The PLL further includes a delay block to process delayed phase error signals generated by the phase detector. The PLL performs hitless clock switching in the event of input clock loss or in response to a command to switch input clocks. The PLL further includes circuitry for estimating and cancelling residual phase errors.

Hitless switching when generating an output clock derived from multiple redundant input clocks

A phase frequency detector (PFD) includes a first circuit portion and a second circuit portion. The first circuit portion receives a reference signal and activates a first error signal if the phase of the reference frequency leads the phase of a feedback signal. The second circuit portion receives the reference and activates a second error signal if the phase of the reference frequency lags the phase of the feedback signal. The first circuit portion is powered by a first power supply, and the second circuit portion is powered by a second power supply. A PLL implemented using the PFD generates a frequency output with minimized jitter.

Reducing errors due to non-linearities caused by a phase frequency detector of a phase locked loop

A divider circuit determines whether an input factor (N) is an even number or an odd number. If N is an even number then the input clock is divided by N/2 to generate an intermediate clock. The intermediate clock is further divided by two to generate a div-by-2 clock, which is provided as the output clock with fifty percent duty cycle. If N is an odd number, the input clock is divided by (N/2&#x2212;0.5) in a first duration and by (N/2+0.5) in a second duration to generate the intermediate clock, which is then divided by two to generate the div-by-2 clock. A delayed clock is generated from the div-by-2 clock, wherein the delayed clock lags the div-by-2 clock by half cycle duration of the input clock. The div-by-2 clock and the delayed clock are combined to generate the output clock with fifty percent duty cycle.

Programmable frequency divider providing a fifty-percent duty-cycle output over a range of divide factors

A programmable frequency divider includes a cascade of frequency-dividing units, each capable of dividing by a first or a second factor. Each unit receives an input clock and generates a divided output clock. Each unit receives a mode control signal that specifies when to divide its input clock by the second factor if a control input allows it, otherwise dividing the input clock by the first factor. The frequency divider is designed to support a range of divide ratios that requires one or more of the units to be non-operative or unused in some intervals. The final divided clock is generated using the mode control signal of the lowest unit in the cascade and the mode control signal of the highest unit that is never set to be non-operative or unused in supporting the range. As a result, duty-cycle variations of the final divided clock are minimized.

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Augusto Marques