International Business Machines Corporation

Augusto J Vega

Alper Buyuktosunoglu

Pradip Bose

Hans Mikael Jacobson

Bryan Savoye Rosenburg

Kyung D Ryu

Robert K Montoye

Michele M Franceschini

Jeffrey Haskell Derby

A central processing unit system includes: a pipeline configured to receive an instruction; and a register file partitioned into one or more subarrays where (i) the register file includes one or more computation elements and (ii) the one or more computation elements are directly connected to one or more subarrays.

Local computation logic embedded in a register file to accelerate programs

Embodiments relate to clustering execution in a processing system. An aspect includes accessing a control flow graph that defines a data dependency and an execution sequence of a plurality of tasks of an application that executes on a plurality of system components. The execution sequence of the tasks in the control flow graph is modified as a clustered control flow graph that clusters active and idle phases of a system component while maintaining the data dependency. The clustered control flow graph is sent to an operating system, where the operating system utilizes the clustered control flow graph for scheduling the tasks.

Clustering execution in a processing system to increase power savings

According to an aspect, dynamic detection of resource management anomalies in a processing system includes collecting data from a plurality of on-line data sources on the processing system. The collected data includes performance data and power consumption data. Anomalous operation of a resource manager of the processing system is identified based on the collected data from the on-line data sources. The identification of the anomalous operation is conducted absent a baseline of reference performance data. A corresponding palliative action is initiated based on identifying the anomalous operation.

Dynamic detection of resource management anomalies in a processing system

According to one embodiment, a method for thread consolidation is provided for a system that includes an operating system and a multi-core processing chip in communication with an accelerator chip. The method includes running an application having software threads on the operating system, mapping the software threads to physical cores in the multi-core processing chip, identifying one or more idle hardware threads in the multi-core processing chip and identifying one or more idle accelerator units in the accelerator chip. The method also includes executing the software threads on the physical cores and the accelerator unit. The method also includes the controller module consolidating the software threads executing on the physical cores, resulting in one or more idle physical cores and a consolidated physical core. The method also includes the controller module activating a power savings mode for the one or more idle physical cores.

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Barcelona, Spain

Augusto J Vega