Micron Technology Incorporated

Other

Stmicroelectronics S.r.l.

Intel Corporation

Ovonyx Inc.

Augusto Benvenuti

Fabio Pellizzer

Haitao Liu

Albert Fayrushin

Giovanni Maria Paolucci

Akira Goda

Agostino Pirovano

Paolo Tessariol

Marcello Mariani

Emilio Camerlenghi

Gianpietro Carnevale

Luca Laurin

Massimo Ernesto Bertuccio

Loris Vendrame

Daniele Cantarelli

Tyler A Lowrey

Giorgio Servalli

Roberto Gastaldi

Antonino Rigano

Giulio Casagrande

Ramanathan Gandhi

Paola Zuliani

Michele Magistretti

Xin Lan

Ferdinando Bedeschi

Daniele Vimercati

Andrea Redaelli

Roberto Bez

Gerald J Barkley

Methods of operating a memory, and memory configured to perform similar methods, might include applying a negative first voltage level to a control gate of a transistor connected between a first node and a string of series-connected memory cells, increasing a voltage level applied to the first node at a particular rate while increasing the voltage level applied to the control gate of the transistor at the particular rate, and in response to the voltage level applied to the first node reaching a particular voltage level, ceasing increasing the voltage level applied to the first node and ceasing increasing the voltage level applied to the control gate of the transistor.

Erasing memory

A transistor comprises a channel region having a frontside and a backside. A gate is adjacent the frontside of the channel region with a gate insulator being between the gate and the channel region. Insulating material having net negative charge is adjacent the backside of the channel region. The insulating material comprises at least one of AlF, HfAlF, AlON, and HfAlON, where 'x', “y”, and “z” are each greater than zero. Other embodiments and aspects are disclosed.

Transistors and arrays of elevationally-extending strings of memory cells

Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a memory cell string having first, second, third, fourth, and fifth memory cells; access lines including first, second, third, fourth, and fifth access lines coupled to the first, second, third, fourth, and fifth memory cells, respectively, and a module. The first memory cell is between the second and third memory cells. The second memory cell is between the first and fourth memory cells. The third memory cell is between the first and fifth memory cells. The module is to couple the first access line to a ground node at a first time of a memory operation, couple the second and third access lines to the ground node at a second time of the operation after the first time, and couple the fourth and fifth access lines to the ground node at a third time of the operation after the second time.

Sequential voltage ramp-down of access lines of non-volatile memory device

Apparatus might include an array of memory cells comprising a plurality of strings of series-connected memory cells and a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to perform a sense operation on a selected memory cell of a string of series-connected memory cells, and to discharge access lines connected to the string of series-connected memory cells in a defined manner following the sense operation.

Apparatus for mitigating program disturb

Some embodiments include a pillar which contains semiconductor material, and which extends primarily along a first direction. A cross-section through the pillar along a second direction orthogonal to the first direction is through the semiconductor material and includes a lateral periphery of the pillar configured as three-sided shape. Some embodiments include an integrated assembly having a vertical stack of alternating first and second levels. The first levels include conductive structures and the second levels are insulative. Channel-material-pillars extend through the vertical stack. Each of the channel-material-pillars has a top-down cross-section which includes a lateral periphery configured as three-sided shape of an equilateral triangle with rounded vertices.

Semiconductor pillars having triangular-shaped lateral peripheries, and integrated assemblies

A transistor comprises a channel region having a frontside and a backside. A gate is adjacent the frontside of the channel region with a gate insulator being between the gate and the channel region. Insulating material having net negative charge is adjacent the backside of the channel region. The insulating material comprises at least one of AlF, HfAlF, AlON, and HfAlON, where 'x', 'y', and &#x201c;z&#x201d; are each greater than zero. Other embodiments and aspects are disclosed.

Methods of operating a memory, and memory configured to perform similar methods, might include applying a positive first voltage level to a first node selectively connected to a string of series-connected memory cells while applying a negative second voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells, and increasing the voltage level applied to the first node to a third voltage level while increasing the voltage level applied to the control gate of the transistor to a fourth voltage level lower than the third voltage level and higher than the first voltage level.

Memories might include an array of memory cells comprising a plurality of strings of series-connected memory cells and a controller for access of the array of memory cells, wherein the controller is configured to perform a sense operation on a particular memory cell of a string of series-connected memory cells, discharge the access line for a second memory cell of the string of series-connected memory cells to a first voltage level and discharge the access line for the particular memory cell to a second voltage level higher than the first voltage level after completion of the sense operation, and discharge the access line for a third memory cell of the string of series-connected memory cells to a third voltage level lower than the second voltage level and higher than the first voltage level after initiating the discharge of the access line for the particular memory cell.

Memories for mitigating program disturb

Methods of operating a memory, and memory configured to perform similar methods, might include performing a sense operation on a particular memory cell of a string of series-connected memory cells, discharging the respective access line for a second memory cell of the string of series-connected memory cells to a first voltage level, discharging the respective access line for the particular memory cell to a second voltage level higher than the first voltage level, and discharging the respective access line for a third memory cell of the string of series-connected memory cells to a third voltage level lower than the second voltage level and higher than the first voltage level.

Apparatus and methods for mitigating program disturb

Embodiments disclosed herein may relate to forming a contact region for an interconnect between a selector transistor and a word-line electrode in a memory device.

Method, system and device for recessed contact in memory array

Growing community of inventors

Lallio, Italy

Augusto Benvenuti