Intel Corporation

Augusto Alcantara

Juan-Carlos Calderon

Jing Ling

Jean-Michel Caia

Soowan Suh

Alejandro Lenero Beracoechea

A method and apparatus for managing memory for time division multiplexed high speed data traffic is provided. The method and apparatus utilize an interleaving approach in association with multiple memory banks, such as within SDRAM, to perform highly efficient data reading and writing. The design issues a first command or access command, such as a read command or write command to one memory bank, followed by an active command to a second memory bank, enabling efficient reading and writing in a multiple data flow environment, such as a SONET/SDH virtual concatenation environment using differential delay compensation.

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Fremont, CA, United States of America

Augusto Alcantara