Micron Technology Incorporated

Intel Corporation

August A Camber

John Rudelic

Mostafa Naguib Abdulla

Sanjeev N Trika

Jawad Basit Khan

Richard Paul Mangold

Anand S Ramalingam

Benjamin Walker

Jonathan Bryan Stern

In one embodiment, an apparatus comprises a storage device to receive, from a computing host, a request to append data to a data log. The storage device is further to identify a memory location after a last segment of the data log, append the data to the data log by writing the data to the memory location after the last segment of the data log, and provide, to the computing host, a key comprising an identification of the memory location at which the data was appended to the data log.

Method and apparatus for improving performance of sequential logging in a storage device

Subject matter disclosed herein relates to memory devices comprising a memory array, a first port to interface with a memory controller directly or indirectly via another memory device, a second port to interface with yet another memory device, and a switch to selectively electrically connect the memory controller to a circuit path leading to the second port or to the memory array, wherein the switch may be responsive to a signal generated by the memory controller.

Multi-device memory serial architecture

A memory device having a memory controller, a main memory with at least a portion comprising persistent memory, and at least two processing entities, wherein the memory controller enables the processing entities to access the main memory according to a cache coherence protocol. The cache coherency protocol can signal when the main memory is being updated and when the update has finished. The processing entities can be configured to wait for the main memory to be updated or can access previously stored memory.

Cache coherence protocol for persistent memories

Subject matter disclosed herein relates to a system of one or more processors that includes persistent memory.

Persistent memory for processor main memory

Subject matter disclosed herein relates to validating memory content in persistent main memory of a processor.

Validating persistent memory content for processor main memory

Subject matter disclosed herein relates to memory devices and security of same.

Security protection for memory content of processor main memory

A program different than an operation system may be utilized to partially update an original image of system code. In one embodiment, operating system code may be adaptively stored and updated within a non-volatile storage device across at least two different memories into at least two code objects based on the relative utilization of the system code in the two code objects. Operating system patching or application and driver updates may be provided without re-writing an entire image of operating system code in some embodiments. The tuning of operating system code storage may be implemented based on a usage pattern of the operating system code on a device in some cases.

Growing community of inventors

Rocklin, CA, United States of America

August A Camber