Syntest Technologies, Inc.

Faraday Technology Corporation

Augusli Kifli

Xiaoqing Wen

Shyh-Horng Lin

Fei-Sheng Hsu

Shih-Chia Kao

Laung-Terng Wang

Hsin-Po Wang

Laung-Terng (l-t) Wang

Shianling Wu

Khader S Abdel-Hafez

Boryau (Jack) Sheu

Wang-Chin Chen

Ming-Tung Chang

Shun-Miin (Sam) Wang

Laung-Terng (l -t) Wang

Hsin-P Wang

A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).

Computer-aided design system to automate scan synthesis at register-transfer level

The invention provides an internal comparison circuits for speeding up the ATPG test. During test, an external test machine transfers original test patterns into at least one scan chain of a chip to be tested. A bi-directional output buffer of the chip also receives the test patterns from the test machine. A comparator of the chip compares the original test patterns from the test machine via the bi-directional output buffer group with scanned-out test patterns from the scan chain, to produce a comparison signal indicating whether the chip passes or fails the test.

High speed ATPG testing circuit and method

A method and apparatus time-division demultiplexes and decompresses a compressed input stimulus provided at a selected data rate R1, into a decompressed stimulus, driven at a selected data rate R2, for driving selected scan chains in a scan-based integrated circuit using a plurality of time-division demultiplexors and time-division multiplexors for shifting stimuli and test responses in and out of high-speed I/O pads in order to reduce test time, test cost, and scan pin count. A synthesis method is also proposed for synthesizing the time-division multiplexors, decompressors, compressors, and time-division multiplexors.

Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuit

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Hsinchu, Taiwan

Augusli Kifli