Xilinx, Inc.

Sony Electronics Inc

Sony Corporation of Japan

Sony Corporation

Dynachip Corporation

Atul V Ghia

Suresh M Menon

Adebabay M Bekele

Paul T Sasaki

Steven P Young

Vasisht Mantra Vadi

Pradip Banerjee

Patrick Chuang

Hare Krishna Verma

Warren E Cory

Jason R Bergendahl

Jian Tan

Ketan Sodha

Qi Zhang

Simon Lau

Austin H Lesea

Trevor J Bauer

Ping-Chen Liu

Philip M Freidin

Philip D Costello

Hassan K Bazargan

Prasad Rau

David P Schultz

Matthew H Klein

Paul Y Wu

Romi Mayder

Arch Zaliznyak

Christopher Paul Wyland

Santiago G Asuncion

Yogendra Kumar Bobra

In one embodiment, an integrated circuit (IC) is presented. The IC includes first and second sets of power distribution lines formed in the IC. The IC includes first and second capacitors formed in one or more layers of the IC. A first plurality of vias couple a first input of the first and second capacitors to the first set of power distribution lines, and a second plurality of vias couple a second input of the first and second capacitors to the second set of power distribution lines. The first capacitor and the first plurality of vias and the second plurality of vias coupled thereto having an equivalent series resistance greater than an equivalent series resistance of the second capacitor and the first plurality of vias and the second plurality of vias coupled thereto.

Power distribution network

A circuit has a programmable mode control section, and a receiver section with first and second input terminals and an output terminal. The method and apparatus involve setting the mode control section to one of first and second states in response to user input, and operating the receiver section in first and second operational mode when the mode control section respectively has the first and second states, wherein in the first operational mode the receiver section provides higher performance and consumes more power than in the second operational mode.

Method and apparatus involving a receiver with a selectable performance characteristic

A clock distribution network having: a backbone clock signal line configured to provide a differential clock signal; multiple branches coupled to the backbone clock signal line for distributing the differential clock signal to multiple programmable function elements; a first leaf node coupled to a first branch, where the first leaf node is configured to provide the differential clock signal to a first programmable function element; and a second leaf node coupled to a second branch, where the second leaf node is configured to provide a single ended clock signal derived from the differential clock signal to a second programmable function element.

Integrated circuit having embedded differential clock tree

Signal distribution of a regional signal is described. An integrated circuit includes a global signal distribution network, a regional signal distribution network and a regional buffer. The regional buffer has an output coupled at an end of the regional signal distribution network. The regional signal distribution network is coupled to a configurable logic block via an interconnect tile. The regional buffer is coupled to a regional clock capable input/output block. Additionally described is a source synchronous interface for regional signal distribution.

Regional signal-distribution network for an integrated circuit

A data alignment and deskewing module includes a delay calibration unit, a data alignment and deskew unit, and a delay unit. The delay calibration unit is operably coupled to generate a reference signal based on a reference clock and a mirrored delay line output signal. The data alignment and deskew unit is operably coupled to determine a delay selection signal based on a delayed and deskewed representation of an input data stream and propagation delay of a line on which the input data stream is received. The delay unit is operably coupled to produce the delayed and deskewed representation of the input data stream based on the reference signal and the delay selection signal.

Data alignment and deskewing module

A clock distribution network having: a main trunk configured to provide a differential clock signal; a plurality of branches coupled to the main trunk for distributing the differential clock signal to a plurality of circuit elements on the integrated circuit; and a plurality of switches coupling the main trunk to the plurality of branches.

Differential clock tree in an integrated circuit

Method and apparatus for phase lock detection is described. More particularly, a phase lock detection circuit () includes a synchronization circuit () coupled to receive a reference signal () and configured to provide a derivative signal (). A phase lock detector () is coupled to receive the reference signal () and the derivative signal () and is configured to provide a cycle lock signal () indicating whether a phase lock exists within a lock window () for a clock cycle.

Phase lock detector

Programmable logic device having an embedded differential clock tree

Signal distribution of a regional signal is described. A programmable logic device includes a global signal distribution network, a regional signal distribution network and a regional buffer. The regional buffer has an output coupled at an end of the regional signal distribution network. The regional signal distribution network is coupled to a configurable logic block via an interconnect tile. The regional buffer is coupled to a regional clock capable input/output block. Additionally described is a source synchronous interface for regional signal distribution.

One or more configurable transceivers can be fabricated on an integrated circuit. The transceivers contain various components having options that can be configured by turning configuration memory cells on or off. The integrated circuit may also contain programmable fabric. Other components in the transceivers can have options that are controlled by the programmable fabric. The integrated circuit may also contain one or more processor cores. The processor core and the transceivers can be connected by a plurality of signal paths that pass through the programmable fabric.

High speed configurable transceiver architecture

A system for distributing a small signal differential signal to a circuit element. The system includes: a first converter configured to convert a first small signal differential signal to a first two phase full CMOS differential signal for input into the differential multiplexer; and a programmable driver circuit configured to boost an output current of the programmable driver circuit at selected frequencies and to convert two phase full CMOS differential signal outputs of the differential multiplexer to a second small signal differential signal.

Differential clocking scheme in an integrated circuit having digital multiplexers

Disclosed are methods and structures for preparing data for transmission over a network. In an embodiment consistent with the OSI network model, transmit and receive CRC generators are moved from the link layer to the physical layer, which frees up valuable programmable logic resources when a programmable logic device is employed to perform the functions of the link layer. The CRC generators of the physical layer comply with a plurality of network communication standards.

Network physical layer with embedded multi-standard CRC generator

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San Jose, CA, United States of America

Atul V Ghia