Intel Corporation

Altera Corporation

University of Massachusetts

Atul Maheshwari

Ankireddy Nalamalpu

Mahesh K Kumashikar

Ram K Krishnamurthy

Dheeraj R Subbareddy

Md Altaf Hossain

Mahesh A Iyer

Steven Hsu

Yuet Li

Mark A Anders

Anshuman Thakur

Alexander Andreev

Gregory F Taylor

Rahul Pal

Greg F Taylor

Kuan-Yueh Shen

David E Duarte

Dheemanth Nagaraj

Wayne Burleson

Sanu K Matthew

Paola Zepeda

Vishak Venkotroman

David Parkhouse

Ian Kuon

Rajesh Vivekanandham

Wayson Lowe

Parker J Rachel

Ban Wong

An integrated circuit includes first and second routing crossbars. The second routing crossbar includes first conductors routed in a first direction in a first conductive layer and second conductors routed in a second direction that is perpendicular to the first direction in a second conductive layer. A first subset of the first conductors is coupled to the first routing crossbar. The first subset of the first conductors is coupled to a second subset of the first conductors through a first subset of the second conductors that is coupled to the first and second subsets of the first conductors through first vias. The second subset of the first conductors is coupled to a second subset of the second conductors to through second vias. At least one of the first conductors is decoupled from another one of the first conductors by third vias.

Circuits and methods for routing crossbars with programmable vias

Systems or methods of the present disclosure may provide efficient power consumption for programmable logic devices based on reducing guardband voltages. A programmable logic device may include circuit monitors to mimic critical paths of an implemented circuit design and generate timing information based on the critical paths. A controller on the programmable logic device may adjust the voltage guardband based on the timing information.

Systems and methods to reduce voltage guardband

A semiconductor device may include a programmable fabric and a processor. The processor may utilize one or more extension architectures. At least one of these extension architectures may be used to integrate and/or embed the programmable fabric into the processor as part of the processor. Systems and methods for transitioning data between the programmable fabric and the processor associated with different clock domains is described.

Flexible instruction set architecture supporting varying frequencies

Systems or methods of the present disclosure may provide for operating a programmable fabric including multiple programmable elements organized into a number of power domains that utilize a common voltage within the respective power domains. A current sensor senses a current of the programmable fabric. When the sensed current has crossed a threshold, the programmable fabric changes the number of power domains.

Switch based on load current

Systems or methods of the present disclosure may provide efficient electric power consumption of programmable logic devices based on providing different voltage levels to different portions (e.g., voltage islands) of the programmable logic device. For example, the programmable logic device may include circuitry to provide different voltage levels to different voltage islands. The programmable logic device may implement and operate logic configurations with different operating parameters using different operating voltages for efficient electric power consumption.

Power management using voltage islands on programmable logic devices

The present disclosure is directed to 3-D stacked architecture for Programmable Fabrics and Central Processing Units (CPUs). The 3-D stacked orientation enables reconfigurability of the fabric, and allows the fabric to function using coarse-grained and fine-grained acceleration for offloading CPU processing. Additionally, the programmable fabric may be able to function to interface with multiple other compute chiplet components in the 3-D stacked orientation. This enables multiple compute components to communicate without the need for offloading the data communications between the compute chiplets.

Three-dimensional stacked programmable logic fabric and processor design architecture

Embodiments of the present disclosure are related to dynamically adjusting a timing and/or power model for a programmable logic device. In particular, the present disclosure is directed to adjusting a timing and/or power model of the programmable logic device that operates at a voltage level that is not other than a predefined voltage defined by a voltage library. A system of the present disclosure may interpolate between voltage levels defined by the voltage libraries to generate a new voltage library for the programmable logic device. A timing and/or power model may be generated for the programmable logic device based on the new voltage library and the programmable logic device may be analyzed using the timing and/or power model at the interpolated voltage. The timing and/or power model may be used to generate a bitstream that is used to program the integrated circuit.

Dynamically scalable timing and power models for programmable logic devices

Methods and systems to control an output frequency relative to a reference frequency. A frequency control system includes a dual-input bias generator to separately receive management and operational controls. The bias generator includes a first bias generator circuit to generate a bias control based on a difference between the management control and a bias feedback reference during a first mode of operation, a second bias generator circuit to generate the bias control based on a difference between the operational control and the bias feedback reference during a second mode of operation, and a bias feedback reference circuit to generate the bias feedback reference based on the bias control. The first mode may include a characterization and/or a start-up mode. The second mode may include an operational mode, such as a feedback-controlled mode.

Frequency control system with dual-input bias generator to separately receive management and operational controls

In one embodiment, an analog-to-digital conversion in an integrated circuit is evaluated by an on-die testing circuit. For example, the on-die test circuitcan characterize one or both of the linearity and monotonicity of the digital-to-analog conversion. The value of a conversion output for a digital input code may be compared to the value of a prior conversion output of a prior step to provide digital difference values for each step of a sweep of digital input codes. Digital difference values may be compared to one or more predetermined limits to provide one or more pass/fail tests on-board the die. Other embodiments are described and claimed.

On-die digital-to-analog conversion testing

An analog-to-digital converter (ADC) suitable for measuring on-die DC or low frequency analog voltages may include a ring oscillator having a group of circuit cells successively and circularly coupled. Under certain circumstances, the ring oscillator may produce an output frequency that corresponds substantially linear to the input voltage. Other embodiments may be disclosed or claimed.

Method, apparatus, and system for measuring analog voltages on die

For one disclosed embodiment, a converter converts 2-bit data into an N-bit value indicating a number of bits in the data that have a predetermined logical value. The converter includes N comparators, each determining whether the number of bits in the data having the predetermined logical value exceeds a respective one of a plurality of reference values. The N-bit value is generated based on the outputs of the comparators. For another disclosed embodiment, a first delay element delays a signal based on a number of bits in a data value having a predetermined logical value, and a second delay element delays the signal based on a number of bits in a reference value having the predetermined logical value. A comparator then generates a bit value based on the delayed signals.

Data converter and a delay threshold comparator

In one embodiment, the present invention includes an oscillator to generate a first frequency and a second frequency. The oscillator includes a plurality of stage cells, each stage cell including a first transistor of a first polarity and a second transistor of a second polarity, each coupled between a first voltage node and a first intermediate node and an inverter coupled to the first intermediate node. In operation, a difference between the first frequency and the second frequency is proportional to a threshold voltage of the second transistor. Other embodiments are described and claimed.

Measuring threshold voltage of transistors in a circuit

In some embodiments, the invention provides a chip with at least one memory circuit that comprises a majority voter circuit with first and second digitally controlled variable delay elements. The first delay element is controlled by data bits that are to be written to a portion of the memory circuit. The majority voter circuit determines if the data bits are to be inverted prior to being written into the memory circuit portion.

Memory with spatially encoded data storage

Disclosed herein are solutions for providing adaptive keeper functionality to dynamic logic circuits. In some embodiments, a programmable keeper circuit is coupled to a register file circuit. Included is a leakage indicator circuit to model leakage in at least a portion of the register file. A control circuit is coupled to the leakage indicator circuit and to the programmable keeper circuit to control the keeper strength in accordance with the modeled leakage. Other embodiments are claimed or otherwise disclosed.

Dynamic logic with adaptive keeper

Returning to FIG.sense circuitrepresents the circuit that must sense the signaling on an interconnect. NMOS deviceis always on so that there is a continuous path to ground whenever PMOS driveris on. Since leakage power is an order of magnitude less than static and dynamic power it can be omitted for clarity, although it should be noted that dynamic power increases with respect to line length since the interconnect capacitance increases as line length increases. Static power is due to flow of static current across the two resistances shown in FIG.interconnect resistanceand the resistance of transistorsandfrom FIG.represented by the resistance of equivalent NMOS transistorof FIG.

Growing community of inventors

Portland, OR, United States of America

Atul Maheshwari