Intel Corporation

Atul Kwatra

Ned M Smith

Francesc Guim Bernat

Kshitij Arun Doshi

Rita H Wouhaybi

Srikathyayani Srikanteswara

Timothy Verrall

Stephen T Palermo

Lokpraveen B Mosur

Sailesh Bissessur

Aniruddha P Joshi

John P Lee

Naveen Lakkakula

Smita Kumar

Pradnyesh S Gudadhe

Sridhar Lakshmanamurthy

Chris MacNamara

Marcos Emanuel Carranza

Yi Zhang

David K Cassetti

Patrick Fleming

Brian Will

Peter Munguia

Thomas M Slaight

Neelam Chandwani

Thijs Metsch

Stephen Doyle

Cesar Martinez-Spessot

Gary J Lavelle

Weiqiang Ma

Zhu Zhou

Karthik Vaithianathan

Xiaotian Gao

Dharmin Y Parikh

Various approaches for the packet processing, and the use of templates for generating modification commands for packet processing, are discussed herein. In an example, operations performed by network packet processing circuitry include: obtaining a stream of packets; obtaining a packet modification template that provides at least one command to insert content within the packets and change the packets according to an output format of a network protocol; receiving parameters to modify the packet modification template; and applying the packet modification template to modify the packets. In further examples, application of the packet modification template is performed using multiple processing components arranged in parallel groups of serial pipelines, each of the serial pipelines applying a portion of the packet modification template within at least a first stage and a second stage in each of the serial pipelines.

Network processor with command-template packet modification engine

Methods and apparatus for hierarchical reinforcement learning (RL) algorithm for network function virtualization (NFV) server power management. A first RL model at a first layer is trained by adjusting a frequency of the core of processor while performing a workload to obtain a first trained RL model. The trained RL model is operated in an inference mode while training a second RL model at a second level in the RL hierarchy by adjusting a frequency of the core and a frequency of processor circuitry external to the core to obtain a second trained RL model. Training may be performed online or offline. The first and second RL models are operated in inference modes during online operations to adjust the frequency of the core and the frequency of the circuitry external to the core while executing software on the plurality of cores of to perform a workload, such as an NFV workload.

Hierarchical reinforcement learning algorithm for NFV server power management

A compression scheme can be selected for an input data stream based on characteristics of the input data stream. For example, when the input data stream is searched for pattern matches, input stream characteristics used to select a compression scheme can include one or more of: type and size of an input stream, a length of a pattern, a distance from a start of where the pattern is to be inserted to the beginning of where the pattern occurred previously, a gap between two pattern matches (including different or same patterns), standard deviation of a length of a pattern, standard deviation of a distance from a start of where the pattern is to be inserted to the beginning of where the pattern occurred previously, or standard deviation of a gap between two pattern matches. Criteria can be established whereby one or more characteristics are used to select a particular encoding scheme.

Selection of data compression technique based on input characteristics

In connection with compression of an input stream, multiple portions of the input stream are searched against previously received portions of the input stream to find any matches of character strings in the previously received portions of the input stream. In some cases, matches of longer character strings, as opposed to shorter character strings, can be selected for inclusion in an encoded stream that is to be compressed. Delayed selection can occur whereby among multiple matches, a match that is longer can be selected for inclusion in the encoded stream and non-selected a character string match is reverted to a literal. A search engine that is searching an input stream to identify a repeat pattern of characters can cease to search for characters that were included in the selected character string match.

Compression scheme with control of search agent activity

In some embodiments a memory controller is disclosed that includes at least one command/address input buffer to receive commands and addresses. The addresses specify a memory bank and a location within the memory bank. An arbiter, coupled to the at least one command/address input buffer, merges commands and addresses from the at least one command/address input buffer and sorts the commands and addresses based on the addresses specified. A plurality of bank buffers, coupled to the arbiter and associated with memory banks, receive commands and addresses for their associated memory banks. A scheduler, coupled to the plurality of bank buffers, groups commands and addresses based on an examination of at least one command and address from the bank buffers. Other embodiments are otherwise disclosed herein.

Memory controller with bank sorting and scheduling

Embodiments of the present invention provide a method and apparatus to allow an I/O controller to alert an external controller using an enhanced SMBus implementation that enables bi-directional capability on SMBALERT#. I/O controller includes an auxiliary control register and alert output enable (AOEN) register. When host sets AOE bit in auxiliary control register, SMBALERT# signal is configured as an output signal with bi-directional functionality. External controller uses an interface command to write to AOEN register and determine events/conditions it wants to be alerted on. SMBALERT# is activated in response to a detected event/condition. In response to SMBALERT#, external controller determines the alert generation condition using byte read commands on the system management bus, and clears SMBALERT#.

Method and apparatus for an I/O controller to alert an external system management controller

Access to internal configuration registers on a computer system's chipset using an external micro-controller is provided. A SMB configuration read command including a register address may be received from an external micro-controller. Access to an internal bus may be requested from a bus arbiter. If internal bus access is granted, the SMB configuration read command may be forwarded to a device including the identified register address using the internal bus. In response to the SMB configuration read command, configuration register values from the device may be received. The configuration register values may be forwarded to the external micro-controller.

Method and apparatus to permit external access to internal configuration registers

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Chandler, AZ, United States of America

Atul Kwatra