Gennum Corporation

Atul Krishna Gupta

Wesley Calvin d'Haene

Vasilis Papanikolaou

Apu Sivadas

Rajiv Kumar Shukla

Kenneth Steven Lazaris-Brunner

Bharat Tailor

John R Francis

Bengt Littmann

Hossein Shakiba

Aapoolcoyuz Biman

Jason R Miller

Dino Toffolon

Linear sample and hold phase detectors are disclosed herein. An example phase detector is coupled to an input data signal and a recovered clock signal and includes a linear phase difference generator circuit and a sample and hold circuit. The linear phase difference generator includes a first input coupled to the input data signal and a second input coupled to the recovered clock signal and outputs a first phase difference signal indicative of the phase difference between the input data signal and the recovered clock signal relative to a rising edge of the input data signal and a second phase difference signal indicative of the phase difference between the input data signal and the recovered clock signal relative to a falling edge of the input data signal. The sample and hold circuit is coupled to the first and second phase difference output signals and samples the voltage levels thereof in response to a first transition of the input data signal and holds the sampled voltage levels until a second transition of the input data signal. Novel clocking circuits using the linear sample and hold phase detector, as well as other types of linear phase detectors, are also disclosed herein in which a gain block non-linearizes the linear phase difference information output from the linear phase detector circuits.

Linear sample and hold phase detector for clocking circuits

In accordance with the teachings described herein, systems and methods are provided for a precision adaptive equalizer. A variable gain equalizer may be used to apply a variable gain to an input signal to generate an equalized output signal. A phase and pattern detector circuit may be coupled in a feedback loop with the variable gain equalizer. The phase and pattern detector circuit may be used to identify a high frequency data pattern in the equalized output signal and compare the high frequency data pattern with a clock signal to detect a high frequency phase error. The phase and pattern detector circuit may be further operable to generate an automatic gain control signal as a function of the high frequency phase error, the automatic gain control signal being fed back to the variable gain equalizer to control the variable gain applied to the input signal.

Precision adaptive equalizer

Transmit amplitude independent adaptive equalizers are provided that compensate for transmission losses in an input signal when the transmit signal amplitude is unknown. Several embodiments are provided, including a first embodiment having an equalizer core, a controllable-swing slicer and an amplitude control loop, a second embodiment having an equalizer core, a fixed-swing slicer and a control loop, a third embodiment having an equalizer core, a variable gain amplifier, and a variable gain amplifier control loop, and a fourth embodiment having an equalizer core, a fixed-swing slicer, a variable gain amplifier, and a variable gain amplifier control loop.

Transmit amplitude independent adaptive equalizer

In accordance with the teachings described herein, systems and methods are provided for automatically correcting duty cycle distortion. A slicer may be used to receive a data input signal and compare the data input signal with a slicer offset voltage to generate a sliced data signal. The slicer may also receive an offset control signal to automatically adjust the slicer offset voltage. A phase detector may be used to receive the sliced data signal and a recovered clock signal and to compare the sliced data signal with the recovered clock signal to generate a rising edge output signal and a falling edge output signal. The rising edge output signal may correspond to a phase difference between a rising edge of the sliced data signal and an edge of the recovered clock signal. The falling edge output signal may correspond to a phase difference between a falling edge of the sliced data signal and an edge of the recovered clock signal. A first feedback circuit may be used to phase-lock the recovered clock signal to the sliced data signal utilizing at least one of the rising edge output signal and the falling edge output signal. At least one of the rising edge output signal and the falling edge output signal may be configured in a second feedback circuit to generate the offset control signal.

System and method for automatically correcting duty cycle distortion

An adaptive equalizer with a large data rate range is provided. The equalizer comprises an equalizer core, a slicer and an automatic gain control (AGC) loop. The equalizer core is coupled to an input signal from a transmission medium and applies a transfer function to the input signal to compensate for losses incurred in the transmission medium in order to generate a core output signal. The equalizer core is also coupled to a bandwidth control signal that controls a bandwidth of the transfer function. The slicer is coupled to the core output signal and converts the core output signal to a digital output signal having a fixed digital output swing that approximates a transmission swing of the input signal prior to transmission over the transmission medium. The AGC loop is coupled to the core output signal and the digital output signal and compares the core output signal with the digital output signal in order to generate the bandwidth control signal.

Adaptive equalizer with large data rate range

An adaptive lock position circuit includes a jitter distribution extremity detector and a phase shifting circuit. The jitter distribution extremity detector receives an input data signal and is operable to compare the input data signal with one or more clock signals derived from a recovered clock signal from a clock and data recovery (CDR) circuit to generate one or more control signals that define the boundaries of a jitter extremity detection window. The phase shifting circuit is coupled in a feedback loop with the jitter distribution extremity detector and receives the one or more control signals from the jitter distribution extremity detector and also receives the recovered clock signal. The phase shifting circuit is operable to shift the phase of the recovered clock signal as a function of the one or more control signals to generate a retiming clock signal such that an edge of the retiming clock signal is interpolated within the jitter extremity detection window.

Adaptive lock position circuit

An improved reclocker circuit and router cell are provided that are particularly useful when configured into a router matrix comprising a plurality of interconnected router cells. The improved reclocker circuit includes an integral N-to-1 multiplexer (MUX), wherein N is at least three. The improved router cell includes the reclocker/MUX circuit, a switch, and a fan-out circuit. A plurality of ports are coupled to the router cell circuitry, including an input port, an output port, a plurality of expansion input ports, and a plurality of expansion output ports. The improved router cell couples either the input port or one the expansion input ports to its output port, and it also couples the input port to each of the expansion output ports. By using the improved router cells in the design of a router matrix, jitter induced by the reclocker circuits is minimized.

Reclocker circuit and router cell

A system for dynamically trimming a voltage controlled oscillator operable to receive a trim signal for adjusting a voltage-to-frequency operating characteristic of the voltage controlled oscillator and receive a tune signal to generate an output signal having an output frequency determined by the voltage-to-frequency operating characteristic includes a trim circuit operable to receive the tune signal and generate the trim signal and increment or decrement the trim signal and condition a change in the trim signal during the increment or decrement so that the voltage-to-frequency operating characteristic of the voltage controlled oscillator drifts from a first voltage-to-frequency operating characteristic to a second voltage-to-frequency operating characteristic.

Dynamically trimmed voltage controlled oscillator

A non-linear phase detector includes a retiming stage and a phase synchronization stage. The retiming stage is coupled to a data signal and a recovered clock signal. The retiming stage is triggered by the recovered clock signal and samples the data signal to generate a retimed data signal and a clock synchronization signal. The phase synchronization stage is coupled to the retimed data signal and the clock synchronization signal. The phase synchronization stage is triggered by the retimed data signal and samples the clock synchronization signal to generate a phase control signal.

Non-linear phase detector

A cable driver is disclosed which provides a substantially linear output signal corresponding to an input signal received by the cable driver on a transmission line. The cable driver includes a number of switches coupled by delay elements with cause the switches to operate in a sequential order in response to an input signal. Each of the switches couples an associated current source to an output port, producing a substantially linear output signal on a transmission line connected to the output port. The substantially linearity of the output signal increases the rate at which data may be transmitted over the transmission line, while permitting the rise and fall time of a specified portion of the output signal to be controlled to ensure that electro-magnetic interference is not produced.

Cable driver with controlled linear rise and fall

A system of resistive end termination and transmission line routing is disclosed for matching the impedance of an IC load to that of a signal source and a transmission line. Each integrated circuit has an internal termination resistor designed to match the characteristic impedance of the transmission line and preferably also the impedance of the source. When the source drives multiple IC devices on a printed circuit board, the devices are cascaded in a chain with the internal resistors of all but the last IC device in the chain bypassed by a short circuit underneath the device, so that a continuous transmission line is provided to the last IC device. The last IC in the chain, which does not have a short circuit underneath it, provides the necessary resistive termination by simply connecting the appropriate pin to a common reference in the circuit. The invention is also applicable to differential applications in which first and second complementary signal sources feed each IC device.

Bus through termination circuit

An improved phase detector for detecting the difference between an information signal and a clock signal is provided. The information signal is divided into a plurality of N divided signals, the data rate of each divided signal being the data rate of the information signal divided by N. A plurality of N variable width difference pulse signals are generated each being responsive to the phase difference between a divided signal and the clock signal. One or more fixed width reference pulse signals having a width proportional to one-half clock period are also generated. A phase error signal is then provided in response to the N difference pulse signals and the one or more reference pulse signals. Preferably, N is equal to 2.sup.M, where M is a positive integer greater than or equal to one.

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Mississauga, Canada

Atul Krishna Gupta