Taiwan Semiconductor Manufacturing Comp. Ltd.

Atul Katoch

Sanjeev Kumar Jain

Ishan Khera

Sahil Preet Singh

Jaspal Singh Shah

A memory circuit includes a global control circuit, a first local control circuit and a first set of word line post-decoder circuits. The global control circuit is configured to generate a first and second set of global pre-decoder signals and a first set of local address signals. The first local control circuit includes a first set of repeater circuits and a first clock pre-decoder circuit. The first set of repeater circuits is configured to generate a first set of local pre-decoder signals in response to the first set of global pre-decoder signals, and a second set of local pre-decoder signals in response to the second set of global pre-decoder signals. The first clock pre-decoder circuit is configured to generate a first and second set of clock signals. The first set of word line post-decoder circuits is configured to generate a first set of word line signals.

Memory circuit and method of operating same

Circuits and methods are provided for a clock generation circuit that includes a first transistor, wherein a gate of the first transistor is connected to a clock signal, a second transistor, connected in parallel to the first transistor, and a driving circuit, coupled to the second transistor, and comprising an input and an output, wherein the input of the driving circuit is connected to the clock signal, the output of the driving circuit is connected to a gate of the second transistor, and the driving circuit is configured to reduce a slew of the clock signal.

Technique to mitigate clock generation failure at high input clock slew

Devices, circuits, and methods are provided. A circuit comprises a tracking word line circuit that is configured to receive an internal clock signal, a turbo signal, and a read enable signal, and to generate a first tracking reading signal and a first tracking writing signal in response to the internal clock signal the turbo signal, and the write enable signal. The circuit also comprises a tracking bit line circuit configured to receive the first tracking reading signal and the first tracking writing signal, wherein the tracking bit line circuit is configured to generate a tracking bit line signal in response to the first tracking reading signal and the first tracking writing signal, wherein the tracking word line circuit is configured to generate a reset signal in response to the tracking bit line signal and transmit the reset signal to the clock generator.

Tracking circuitry and memory devices including the same

A memory circuit includes a set of memory cells configured to store data, and a local input output (LIO) circuit coupled to a global bit line and the set of memory cells. The LIO circuit includes a sense amplifier, a driver circuit and a booster circuit. The sense amplifier is configured to sense a first signal in response to at least a sense amplifier signal. The first signal corresponds to a value of the data stored in the set of memory cells. The driver circuit is configured to generate a global bit line signal in response to at least the first signal or an inverted first signal. The booster circuit is coupled to the driver circuit and the global bit line, and configured to adjust the global bit line signal in response to a delayed global bit line signal.

A memory circuit includes a plurality of word lines, a word line driver coupled to a first end of the plurality of word lines and configured to activate each word line of the plurality of word lines, a local I/O circuit configured to generate a pulse signal corresponding to the word line driver activating any word line of the plurality of word lines, a first node configured to carry a first power supply voltage, and a booster circuit coupled to a second end of the plurality of word lines, the local I/O circuit, and the first node. The booster circuit is configured to couple each word line of the plurality of word lines to the first node responsive to the pulse signal and to the corresponding word line being activated by the word line driver.

Word line booster circuit and method

A memory circuit includes a global control circuit, a first local control circuit, and a first set of word line post-decoder circuits coupled to a first set of memory cells that is configured to store a first set of data. The global control circuit is configured to generate a first and second set of global pre-decoder signals, and a first set of local address signals. The first local control circuit includes a first set of repeater circuits and a first clock pre-decoder circuit. The first set of repeater circuits is configured to generate a first and second set of local pre-decoder signals in response to the corresponding first and second set of global pre-decoder signals. The first clock pre-decoder circuit is configured to generate a first and second set of clock signals in response to the first set of local address signals and the first clock signal.

A memory circuit includes a plurality of word lines, a word line driver coupled to the plurality of word lines, and a booster circuit coupled to the plurality of word lines. The word line driver is configured to output a first word line signal on a first word line of the plurality of word lines, and the booster circuit includes a first node configured to carry a first power supply voltage and is configured to couple the first word line of the plurality of word lines to the first node responsive to a pulse signal and the first word line signal.

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Hsinchu, Taiwan

Atul Katoch