Teledyne Licensing, LLC

Teledyne Scientific and Imaging, LLC

United States of America As Represented by the Administrator of Nasa

Atul Joshi

Vincent Douence

Hakan Durmus

John C Stevens

David J Chiaverini

Jeffrey DeNatale

William E Tennant

Stefan Clemens Lauxtermann

Adam Lee

Selim Eminoglu

Markus Loose

Per-Olov Pettersson

Edward S Cheng

Angelika Kononenko

Daniel P Kelly

Brian S Smith

Greg T Alkire

Gananath Wijeratne

A custom application-specific integrated circuit (ASIC) may provide strong signal integrity while reducing the load to a thermal system. Control and analog-to-digital conversion may be pushed into components close to the detector to maximize signal integrity. Processing functions may be performed at relatively high temperature, or the highest allowable temperatures, simplifying the system-level thermal design by not cooling components that do not require such cooling to function.

Detector control and data acquisition with custom application specific integrated circuit (ASIC)

A fast-settling line driver circuit capable of high-speed operation. The line driver is particularly well-suited for operation in a high-resolution imaging system. The line driver circuit comprises a signal amplifier that is configured in a negative feedback loop and connected to a bus line through a switch network. The switch network is disposed inside the feedback loop while the line driver is transmitting a signal onto the bus line. This configuration reduces the settling time of the line driver by substantially eliminating the effect of the switch resistance on the RC time constant. The line driver also comprises offset cancellation and presettle circuits that improve the integrity of the output signal and reduce the power consumption of the system.

Fast-settling line driver design for high resolution video IR and visible images

Embodiments of a read-out integrated circuit (ROIC) include a plurality of unit cells. Each unit cell includes a bias subsystem, a reset switch, at least one integration capacitor, and at least one read switch. A focal plane array includes a plurality of photo detectors disposed in a grid and a ROIC. A column buffer includes a first buffer subsystem, a feedback subsystem, a first and second correlated double sampling subsystem, and a second buffer subsystem. A ROIC includes at least one integration subsystem having a transistor subsection, a poly silicon layer, and a plurality of active layer sections.

Multi-color read-out integrated circuit

Fast-settling line driver design for high resolution video IR and visible imagers

A semiconductor device and method for fabricating the same is provided. The semiconductor device includes a substrate, at least one capacitor, an active circuit and a power plane. The substrate has a first cavity formed through a first surface to a first depth and a second cavity formed through a second surface to a second depth. The first and second cavities forming a via hole through the substrate. The at least one capacitor includes a first conductive material layer deposited in the via hole, a first isolation material layer deposited over the first conductive material layer, and a second conductive material layer deposited over the first isolation material layer. The active circuit adjacent the first surface and electrically coupled to the at least one capacitor, and the power plane adjacent the second surface and electrically coupled to the at least one capacitor to provide power conditioning to the active circuit.

Power distribution for CMOS circuits using in-substrate decoupling capacitors and back side metal layers

An imaging system implementing a scheme for enhancing the dynamic range of the device. An array of radiation detecting pixels produces an output in response to a stimulus. The signal from each pixel is read once for evaluation. If the voltage at an individual pixel satisfies a programmed condition, such as exceeding a predetermined threshold voltage at a particular time, that pixel is reset and begins producing an output signal anew. If the pixel output signal does not satisfy the condition, it is allowed to continue producing the signal without being reset. After the evaluation read, all of the pixels are then read row by row into a buffer and digitally processed. A memory register tracks which pixels have been reset, and the corresponding output signals are adjusted accordingly. This scheme allows the system to process input signals across a broader range of intensity without losing information due to pixel saturation or sacrificing sensitivity.

Dynamic range enhancement scheme for imagers

A high-order delta-sigma analog-to-digital converter. A plurality of stages are connected to accept an analog input signal and produce a digital output signal. Each stage has a resettable &#x394;-&#x3a3; converter of second order or higher. Resetting each stage before accepting a new input purges the integrators of any information related to the previous input, allowing step inputs to the system. The stability of the converter is ensured using local feedback loops at each stage. Each stage provides a digital representation of a portion of the analog input signal. A decimation filter receives the digital signals from the stages and arranges them into the digital output signal.

Resettable high order delta-sigma analog to digital converter

An imaging system includes a row and column array of active pixels, each having an associated pitch. In response to respective control signals, each pixel outputs a reset level which includes noise components, or a signal level which includes signal and noise components. Multiple column buffers, each having a pitch equal to or less than that of a pixel, convey the outputs of respective pixel columns to a bus line. Each buffer comprises 'odd' and 'even' S&H/CDS circuits, which process the pixel outputs of odd and even rows, respectively. Each S&H/CDS circuit subtracts pixel reset level from signal level to produce an output in which correlated noise is suppressed. Each column buffer includes a buffer amplifier which conveys the output to the bus line. A gain amplifier separate from the column buffers is coupled to the bus line such that it amplifies the outputs of a multiple column buffers.

Imaging system with low noise pixel array column buffer

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Thousand Oaks, CA, United States of America

Atul Joshi