Samsung Electronics Co., Ltd.

Freescale Semiconductor,inc.

Nxp Usa, Inc.

Atul Gupta

Amit Goel

Ankur Sharma

Ajay Kumar

Ajay K Gaite

Sachin Kumar Gupta

Naresh Dhamija

Risi Jaiswal

Llamparidhi L

Gaurav Garg

Utkarsh Pathak

Rajeev Sharma

Embodiments herein disclose a method for optimizing power consumption in an electronic device comprising a plurality of RATs. The method includes determining a system bandwidth of the plurality of RATs available in the electronic device and mapping at least one portion of the system bandwidth to at least one power consumption level of a set of power consumption levels of the electronic device. Further, the method includes distributing the at least one portion of the system bandwidth across the plurality of RATs based on the at least one mapped power consumption level of the set of power consumption levels of the electronic device. Further, the method includes enforcing the distributed system bandwidth across the plurality of RATs in the electronic device and enabling at least one application to use the distributed system bandwidth across the plurality of RATs in the electronic device.

Method and electronic device for optimizing power consumption in electronic device

An image processing system for convolving an image includes processing circuitry that is configured to retrieve the image including a set of rows, a merged kernel, multiple skip values and a pixel base address. The merged kernel includes all non-zero coefficients of a set of kernels. Each skip value corresponds to a location offset of each non-zero coefficient with respect to a previous non-zero coefficient. Further, the processing circuitry is configured to execute a multiply-accumulate (MAC) instruction and a load instruction parallelly in one clock cycle for multiple times, on the set of rows and the merged kernel to convolve the image with the merged kernel. Each row on which the MAC and load instructions are executed is associated with a corresponding non-zero coefficient and a corresponding skip value. The load instruction is executed based on the pixel base address, the corresponding skip value, and a width of each row.

System and method for convolving image with sparse kernels

A system for convolving an image includes a processing circuitry that retrieves the image including a set of rows, and a set of kernels, and merges serially all columns of each kernel, to generate a merged kernel. The processing circuitry executes parallelly multiple times, a multiply-accumulate (MAC) instruction on a row loaded in a corresponding vector register and a corresponding coefficient of the merged kernel and a load instruction on a subsequent row in one clock cycle. In the same clock cycle based on the MAC instruction, a logical shift operation is executed on the merged kernel to shift a current coefficient of the merged kernel with a subsequent coefficient such that the MAC instruction is executed on the subsequent row and the subsequent coefficient in the next clock cycle. Thus, each clock cycle is utilized by the system for executing both the MAC and load instructions.

System and method for convolving an image

A method and a system for operating a flexible computing-device is provided. The method is executed by the system and includes determining at least one bending axis of a computing-device based on a type of application selected by a user. Based on an activation-instruction received from the user, a bending-axis selected from one or more bending axis is also activated. Further, at least one user-input directed to the device is received, based upon which a user-interface of the application uniquely linked to the activated bending-axis is rendered. Such user-interface has at least one designated-control to operate the application.

Method and system for operating a flexible computing-device according to different functionality based on bending axis

A DLL includes a phase detector, a counter, a delay circuit, and a false-lock detection and recovery circuit. The false-lock detection and recovery circuit checks whether the DLL is in a true-lock condition or not, based on an average of a phase difference between a clock signal and an intermediate clock signal. The intermediate clock signal is generated by the delay circuit based on a count value generated by the counter and a select signal generated by the false-lock detection and recovery circuit. The false-lock detection and recovery circuit generates and provides a control signal to the counter. Based on the control signal, the counter modifies the count on which a delay between the clock signal and an output signal of the DLL depends when the DLL is not in the true-lock condition.

Delay-locked loop with false-lock detection and recovery circuit

A method for compensating for variations in timing of data sent to a processor on data bit lines relative to a strobe clock sent to the processor on a strobe clock line that can be used in a dual data rate (DDR) memory identifies discrete minimum and maximum time offset values for test data in selected data bit patterns for the data bit lines. The discrete minimum time offset value is the minimum timing adjustment required to allow the processor to receive the data in a steady-state condition during a data valid window of the strobe clock and the discrete maximum time offset value is a maximum timing adjustment required to allow the processor to receive the data in a steady-state condition during a data valid window of the strobe clock. The discrete minimum and maximum time offset values identify a valid range when the data bit lines supply data in a steady-state condition for latching into the processor by the strobe clock.

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Noida, India

Atul Gupta