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Infineon Technologies North America Corp.

Atul Champaklal Ajmera

Dominic Joseph Schepis

Kevin K Chan

Erin C Jones

Ghavam G Shahidi

Andres Bryant

Herbert Lei Ho

Shreesh Narasimha

Renee Tong Mo

David M Dobuzinsky

Edward P Maciejewski

Robert J Miller

Michael Abramovich Gribelyuk

Young Way Teh

Erwin Hammerl

Michael D Steigerwalt

Victor Ku

Samuel C Ramac

Stephen G Fugardi

James F Moseman

Percy V Gilbert

Devendra K Sadana

Bruce Bennett Doris

Jeffrey P Gambino

Effendi Leobandung

Guy M Cohen

Oleg Gluschenkov

Son Van Nguyen

Cyril Cabral, Jr

Zhijiong Luo

Christian Lavoie

Xiangdong Chen

Omer H Dokumaci

Evgeni Petrovich Gousev

Viraj Yashawant Sardesai

Werner A Rausch

Fariborz Assaderaghi

Anthony Gene Domenicucci

Roy Arthur Carruthers

Klaus D Beyer

Christopher Peter D'Emic

Christopher Carr Parks

Ronnen Andrew Roy

Tomio Katata

Christine Dehm

Herbert Palm

Christopher V Baiocco

Heemyong Park

George G Gifford

Joseph S Newbury

Karanam Balasubramanyam

Stephen K Loh

Ka Hing Fung

Paul Michael Kozlowski

Wenzhi Gao

Shang-Bin Ko

Ka Hing (Samuel) Fung

Rober J Miller

J Herbert Palm

Process for enhancing strain in a channel with a stress liner, spacer, process for forming integrated circuit and integrated circuit. A first spacer composed of an first oxide and first nitride layer is applied to a gate electrode on a substrate, and a second spacer composed of a second oxide and second nitride layer is applied. Deep implanting of source and drain in the substrate occurs, and removal of the second nitride, second oxide, and first nitride layers.

Spacer and process to enhance the strain in the channel with stress liner

A method of forming a semiconductor device that embeds an L-shaped spacer is provided. The method includes defining an L-shaped spacer on each side of a gate region of a substrate and embedding the L-shaped spacers in an oxide layer so that the oxide layer extends over a portion of the substrate a predetermined distance from a lateral edge of the L-shaped spacer. And removing oxide layers to expose the L-shape spacers.

Methods of forming semiconductor devices using embedded L-shape spacers

A structure and method of fabrication for MOSFET devices with a polycrystalline SiGe junction is disclosed. Ge is selectively grown on Si while Si is selectively grown on Ge. Alternating depositions of Ge and Si layers yield the SiGe junction. The deposited layers are doped, and subsequently the dopants outdiffused into the device body. A thin porous oxide layer between the polycrystalline Ge and Si layers enhances the isotropy of the SiGe junctions.

Polycrystalline SiGe Junctions for advanced devices

Polycrystalline SiGe junctions for advanced devices

A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric below a conductor with vertical sidewalls, a dielectric layer is formed thereover and over the substrate surfaces. Respective nitride spacer elements overlying the dielectric layer are formed at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample (the gate stack, the spacer elements at each gate sidewall, and substrate surfaces) and subsequently removed by an etch process such that only a portion of said nitride film (the 'plug') remains. The plug seals and encapsulates the dielectric layer underlying each said spacer, thus preventing the dielectric material from being undercut during the subsequent pre-silicide clean process. By preventing undercut, this invention also prevents the etch-stop film (deposited prior to contact formation) from coming into contact with the gate oxide. Thus, the integration of thin-spacer transistor geometries, which are required for improving transistor drive current, is enabled.

Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs

The present invention provides a method of formed a nitrided surface layer atop a polysilicon gate electrode that inhibits the growth of an epi silicon layer thereon. Specifically, the method of the present invention includes the steps of: forming a polysilicon layer atop a gate dielectric layer, forming a nitrided surface layer on the polysilicon layer; selectively removing portions of the nitrided surface layer and the polysilicon layer stopping on the gate dielectric layer, while leaving a patterned stack of the nitrided surface layer and the polysilicon layer on the gate dielectric layer; forming sidewall spacers on at least exposed vertical sidewalls of polysilicon layer; removing portions of the gate dielectric layer not protected by the sidewall spacers; and growing an epi silicon layer on exposed horizontal surfaces of an underlying semiconductor substrate.

Surface engineering to prevent epi growth on gate poly during selective epi processing

A method for forming an ultra thin gate dielectric for an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the method includes forming an initial nitride layer upon a substrate by rapidly heating the substrate in the presence of an ammonia (NH ) gas, and then re-oxidizing the initial nitride layer by rapidly heating the initial nitride layer in the presence of a nitric oxide (NO) gas, thereby forming an oxynitride layer. The oxynitride layer has a nitrogen concentration therein of at about 1.0&times;10 atoms/cm to about 6.0&times;10 atoms/cm , and has a thickness which may be controlled within a sub 10 &angst; range.

Method for forming heavy nitrogen-doped ultra thin oxynitride gate dielectrics

In order to prevent abnormal oxidation of the side wall of a polycide gate conductor layer in the oxidation heat treatment process after the RIE processing of the polycide gate conductor layer in a semiconductor memory cell, the heat treatment for oxidizing the side wall of the polycide gate conductor layer is conducted in two steps with different conditions. By conducting the first heat treatment process in an inert atmosphere, a thin oxide film is formed on the side wall of the polycide tungsten/gate conductor layer. Then by conducting the second heat treatment process in an atmosphere with a strong oxidizing property, a thick oxide film without abnormal oxidation can be formed.

Method of forming an oxide film on a gate side wall of a gate structure

A method for forming an isolation trench in a silicon or silicon-on-insulator substrate is described in which a trench is formed in the semiconductor structure (containing a multiple layer structure of Si, SiO , and SiN layers) and an undoped polysilicon layer is deposited on the bottom and sidewalls of the trench and on the surface of the region adjacent to the trench. A substantial portion of the trench is left unfilled by the undoped polysilicon layer deposited. The polysilicon layer is thermally oxidized to form a thermal oxide that fills the trench and thereby avoids forming a birds-beak formation of the thermal oxide above the sidewalls of the trench. The isolation structure may be planarized by either removing the polysilicon layer from the region adjacent to the trench before oxidation or later removing the oxide from the SiN layer and adjusting height of the oxide in the trench. Alternatively, either a doped polysilicon layer or a doped SiO layer may be formed above the silicon nitride layer before the undoped polysilicon layer is deposited. In this case, the isolation structure is heat treated prior to oxidization to drive dopants from the doped layer into the undoped polysilicon layer, thereby forming a secondarily doped polysilicon layer from the undoped polysilicon layer. The doped layers are then removed by selective wet etching and expose the silicon nitride layer prior to oxidation.

Shallow trench isolation for thin silicon/silicon-on-insulator substrates by utilizing polysilicon

A CMOS structure and method of achieving self-aligned raised source/drain for CMOS structures on SOI without relying on selective epitaxial growth of silicon. In the method, CMOS structures are provided by performing sacrificial oxidation so that oxidation occurs on the surface of both the SOI and BOX interface. This allows for oxide spacer formation for gate-to-source/drain isolation which makes possible raised source/drain fabrication without increasing contact resistance.

CMOS structure with non-epitaxial raised source/drain and self-aligned gate and method of manufacture

The present invention provides a method of preparing a Si-based metal-insulator-semiconductor (MIS) transistor which prevents the polycrystalline grains of the gate conductor from getting significantly larger by reducing the thermal budget of the sidewall oxidation process. The thermal budget of the inventive sidewall oxidation process is reduced one or two orders of magnitude over conventional prior art sidewall oxidation processes by utilizing atomic oxygen as the oxidizing ambient. The present invention also provides Si-based MIS transistors having a gate conductor having grain sizes of about 0.1, preferably 0.05, &mgr;m or less.

Method of improving gate activation by employing atomic oxygen enhanced oxidation

A method for forming a substrate contact in a substrate that includes a silicon on insulator region. A shallow isolation trench is formed in the silicon on insulator substrate. The shallow isolation trench is filled. Photoresist is deposited on the substrate. A contact trench is formed in the substrate through the filled shallow isolation trench, silicon on insulator, and silicon substrate underlying the silicon on insulator region. The contact trench is filled, wherein the material filling the contact trench forms a contact to the silicon substrate.

Method of integrating substrate contact on SOI wafers with STI process

An innovative MOSFET having a raised source drain (RSD) is constructed prior to implanting source-drain dopants. The RSD structure thus built has a distinct advantage in that the offset from the RSD to the MOSFET channel is fully adjustable to minimize the overlap capacitance in the device. The RSD construction uses a selective epitaxial process to effectively reduce the drain-source resistance. This improvement is even more significant in thin-film SOI technology. Using an RSD, the film outside the channel area thickens which, in turn, reduces the parasitic resistance. The method of constructing such a structure includes the steps of: forming a notch gate on a top surface of a substrate; covering the notch gate and the top surface of the substrate with a conformal dielectric film; etching the dielectric film to expose an upper surface of the notch gate and selected exposed areas of the substrate; selectively growing silicon on the etched surface of the gate notch and on the etched surface of the substrate; implanting doping to form a drain-source area; forming spacers on the vertical walls of the notch gate; and forming a salicide on the notch gate and on the source and drain areas. The MOSFET device may be alternately be built without the formation of spacers.

Method for forming notch gate having self-aligned raised source/drain structure

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Wappingers Falls, NY, United States of America

Atul Champaklal Ajmera