International Business Machines Corporation

Samsung Electronics Co., Ltd.

Lenovo (singapore) Pte. Ltd.

Atsuya Okazaki

Masatoshi Ishii

Nobuyuki Ohba

Yasunao Katayama

Kohji Hosokawa

Junka Okazawa

Takayuki Osogami

Takeo Yasuda

Seiji Munetoh

Akiyo Iwashina

Yasushi Negishi

Megumi Ito

Tadayuki Okada

Seiji Muneto

A system may include a power supply or regulator connected to a target block with a ground line and a power line, a first switch in the power line, a sense line connected between the power supply for the regulator and a sense point on the power line at the target block side of the first switch, a second switch in the sense line, a third switch connected between the power line at the target block side of the first switch and the ground line, and a control circuit for generating a control signals to the first switch, the second switch, and the third switch.

Ir drop compensation

A computer-implemented method for processing signals is provided including advantageously generating a temporally continuous weighted pulse position modulation (CW PPM) duration signal from an input analog signal, converting the CW PPM duration signal to a memory access signal, executing a multiply and accumulate (MAC) operation with the memory access signal, and advantageously generating the input analog signal from a result of the MAC operation by an activation function (AF).

Data transfer with continuous weighted PPM duration signal

A neuromorphic chip includes synaptic cells including respective resistive devices, axon lines, dendrite lines and switches. The synaptic cells are connected to the axon lines and dendrite lines to form a crossbar array. The axon lines are configured to receive input data and to supply the input data to the synaptic cells. The dendrite lines are configured to receive output data and to supply the output data via one or more respective output lines. A given one of the switches is configured to connect an input terminal to one or more input lines and to changeably connect its one or more output terminals to a given one or more axon lines.

Neuromorphic chip for updating precise synaptic weight values

A synapse memory system includes synapse memory cells, each of which includes a non-volatile random access memory (NVRAM). Each synapse memory cell is configured to store a weight value according to an output level of a write signal. A write portion is configured to write the weight value to each synapse memory cell and includes a write driver and an output controller. The write driver is configured to output the write signal to each synapse memory cell. The output controller is configured to control the output level of the write signal of the write driver. Read drivers are configured to read the weight value stored in the synapse memory cells. The output controller is configured to control the output level of the write signal in updating the weight value in the synapse memory cell, to compensate for weight value variation according to a device characteristic of the NVRAM.

Synapse weight update compensation

A spiking neural network device including a spiking neural network circuit including a crossbar array of plural synapses; plural axons connected with the spiking neural network circuit, the plural axons receiving input of a spike signal; and plural Poisson spike generators respectively provided for the plural axons. Each Poisson spike generator can be set whether or not to emit the spike signal based on an input signal to be processed, and each Poisson spike generator can, be set to emit the spike signal being configured to generate a Poisson spike train different from each other. and supply the Poisson spike train to a corresponding one of the plural axons.

On-chip Poisson spike generation

A method for identifying, in a system including two or more computing devices that are able to communicate with each other, with each computing device having with a cache and connected to a corresponding memory, a computing device accessing one of the memories, includes monitoring memory access to any of the memories; monitoring cache coherency commands between computing devices; and identifying the computing device accessing one of the memories by using information related to the memory access and cache coherency commands.

Identification of a computing device accessing a shared memory

An analog Magnetoresistive Random Access Memory (MRAM) cell is provided. The analog MRAM cell includes a magnetic free layer having a first domain having a first magnetization direction, a second domain having a second magnetization direction opposite to the first magnetization direction and a domain wall located between the first domain and the second domain. The analog MRAM cell further includes a magnetically pinned layer. The analog MRAM cell also includes an insulating tunnel barrier between the magnetic free layer and the magnetically pinned layer. The analog MRAM cell additionally includes an electrode located adjacent to the magnetic free layer configured to generate heat by supplying current to decrease a conductance of the magnetic free layer.

NVM synaptic element with gradual reset capability

A neuromorphic electric system includes a network of plural neuron circuits connected in series and in parallel to form plural layers. Each of the plural neuron circuits includes: a soma circuit that stores a charge supplied thereto and outputs a spike signal; and plural synapse circuits that supply a charge to the soma circuit according to a spike signal fed to the synapse circuits, a number of the plural synapse circuits being one more than a number of plural neuron circuits in a prior layer outputting the spike signal to the synapse circuits. One of the plural synapse circuits supplies a charge to the soma circuit in response to receiving a series of pulse signals, and the others of the plural synapse circuits supply a charge to the soma circuit in response to receiving a spike signal from corresponding neuron circuits in the prior layer.

Monitoring potential of neuron circuits

A computer-implemented method is provided for refreshing cells in a Non-Volatile Memory (NVM)-based neuromorphic circuit wherein synapses are each composed of a respective cell pair formed from a respective Gp cell and a respective Gm cell of the cells. The method includes randomly selecting multiple neurons and reading a conductance of any of the synapses connected to the multiple neurons. The method further includes selecting any of the synapses connected to the selected multiple neurons for which the Gm conductance has reached a maximum conductance. The method also includes resetting the Gp cell and Gm cell of the selected synapses, and setting, at most, one of the Gp cell and Gm cell of each of the selected synapses to recover an effective total weight of each of the selected synapses.

Scalable refresh for asymmetric non-volatile memory-based neuromorphic circuits

A neuromorphic circuit, chip, and method are provided. The neuromorphic circuit includes a crossbar synaptic array cell. The crossbar synaptic array cell includes a Complimentary Metal-Oxide-Semiconductor (CMOS) transistor having an on-resistance controlled by a gate voltage of the CMOS transistor to update a weight of the crossbar synaptic array cell. The gate voltage of the CMOS transistor is controlled by performing a charge sharing technique that updates the weight of the crossbar synaptic array cell using non-overlapping pulses on control lines that are aligned with a set of row lines and a set of column lines.

Linearly weight updatable CMOS synaptic array without cell location dependence

A method is provided of initializing a chip having synaptic NVRAM cells connected row-wise by word lines and column-wise by bit lines. The method includes selecting each word line through a row decoder connected to all word lines to switch all synaptic NVRAM cells of the selected lines. The method includes driving, on the selected lines, a wave generated by a PLL circuit connected to the row decoder. The method includes generating standing waves from the wave on the selected lines by implementing a resonance detection point at an input end of each word line. The method includes applying a write voltage on all bit lines through a column decoder connected to all bit lines. The method includes simultaneously driving each of the synaptic NVRAM cells of the selected lines by different writing currents for different durations in order to set different analog values to the synaptic NVRAM cells.

Memory data randomizer

A method is provided of initializing a chip having synaptic NVRAM cells connected row-wise by word lines and column-wise by bit lines. The method includes driving, on selected word lines from among the word lines, a wave generated by a PLL circuit. The method includes generating standing waves from the wave on the selected lines by implementing a resonance detection point at an input end of each word line. The method includes applying a write voltage on all bit lines. The method includes simultaneously driving each of the synaptic NVRAM cells of the selected lines by different writing currents for different durations in order to set different analog values to the synaptic NVRAM cells.

A neuromorphic circuit, chip, and method are provided. The neuromorphic circuit includes a crossbar synaptic array cell. The crossbar synaptic array cell includes a Complimentary Metal-Oxide-Semiconductor (CMOS) transistor having an on-resistance controlled by a gate voltage of the CMOS transistor to update a weight of the crossbar synaptic array cell. The neuromorphic circuit further includes a set of row-lines respectively connecting the synaptic array cell in series to a plurality of pre-synaptic neurons at first ends thereof. The neuromorphic circuit also includes a set of column-lines respectively connecting the synaptic array cell in series to a plurality of post-synaptic neurons at second ends thereof. The gate voltage of the CMOS transistor is controlled by performing a charge sharing technique that updates the weight of the crossbar synaptic array cell using non-overlapping pulses on control lines that are aligned with the set of row lines and the set of column lines.

A computer-implemented method is provided for refreshing cells in a Non-Volatile Memory (NVM)-based neuromorphic circuit wherein synapses are each composed of a respective cell pair formed from a respective Gp cell and a respective Gm cell of the cells. The method includes randomly selecting multiple neurons and reading a Gp conductance and a Gm conductance of any of the synapses connected to the multiple neurons. The method further includes selecting any of the synapses connected to the selected multiple neurons for which any of the Gp conductance or the Gm conductance have reached a maximum conductance. The method also includes resetting the Gp cell and Gm cell of the selected synapses, and setting, at most, one of the Gp cell and Gm cell of each of the selected synapses to recover an effective total weight of each of the selected synapses.

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Tokyo, Japan

Atsuya Okazaki