Mitsubishi Electric Corporation

Nec Corporation

Renesas Technology Corp.

Atsushi Yoshikawa

Akinobu Sugiyama

Nobutaka Nakamura

Masataka Shirozono

Yoichi Okubo

Takanori Matsunaga

Kohei Mori

Yasuhiko Hagihara

In a remote parking device, a remote control receiver receives remote operation signals including remote parking commands of a subject vehicle from a plurality of remote controllers. A sensor information receiver receives sensor information including surrounding information obtained in a surrounding information sensor in the subject vehicle and vehicle information obtained in a vehicle information sensor in the subject vehicle. When the plurality of remote operation signals including the remote parking commands are received at the same time, a priority determination part determines priority of each of the plurality of remote parking commands included in the plurality of remote operation signals based on information obtained from the plurality of remote operation signals. A remote parking controller controls a remote parking of the subject vehicle based on the remote parking command having highest priority and the sensor information.

Remote parking device and remote parking method

A vehicle energy management device has a vehicle information receiver to receive vehicle information including a vehicle speed and a state of charge of a battery, a route information receiver to receive route information to a destination, and a processing circuitry. The processing circuitry is configured to perform: a vehicle information acquisition process of acquiring vehicle information including at least information on a vehicle speed and a state of charge of the battery; a route information acquisition process of acquiring route information to the destination; an optimal plan calculation process of making a target vehicle speed plan for the destination and a driving necessity plan for a motor, an engine, and a generator on the basis of the route information and the vehicle information; and a vehicle control process of controlling the motor, the engine, and the generator on the basis of the driving necessity plan.

Vehicle energy management device

When a following vehicle approaches a host vehicle, a following vehicle warning unit that issues a warning to the following vehicle on the basis of the likelihood of a front end collision, calculated by a front end collision likelihood calculation unit and the likelihood of a rear end collision, calculated by a rear end collision likelihood calculation unit, issues a warning to the following vehicle before activating a brake apparatus of the host vehicle at a brake force determined by a braking processing determination unit that determines a brake force required to prevent a collision between the host vehicle and a frontward obstruction on the basis of the likelihood of a front end collision.

Vehicle collision prevention apparatus

A vehicle energy management device includes: an energy consumption related information acquisition unit which acquires energy consumption related information that is information related to energy consumption of an own vehicle in each of traveling sections; an energy consumption related information correction unit which corrects the energy consumption related information; and a control plan production unit which produces a control plan for vehicle instruments based on an estimated value of an energy consumption amount of each of the vehicle instruments calculated by using the corrected energy consumption related information. The energy consumption related information correction unit corrects the energy consumption related information based on a result of comparing an actually measured value of traveling characteristics of the own vehicle in each of the road categories and a statistical result of traveling characteristics of a plurality of general vehicles in each of the traveling sections.

Two paths (arrival and required paths) as a target of analysis are united into a single path, and an on-chip random variation component &#x3c3;r about a plurality of nodes of the single path is calculated. Next, an on-chip variation component &#x3c3;chip is calculated on the basis of the on-chip random variation component &#x3c3;r and an on-chip systematic variation component &#x3c3;s. Subsequently, a delay variation Docv is calculated on the basis of a reference delay Dbase of the entire path and the on-chip variation component &#x3c3;chip.

Method and program for designing semiconductor integrated circuits, and semiconductor integrated circuit designing apparatus

The present invention provides for adjusting the delay time interval of an input signal by controlling the internal register value and internal signal in a semiconductor integrated circuit device, or an external signal. The invention comprises a first gate arrayfor carrying out fine adjustment of the delay time interval of the input signal, capacitancestoandtoconnected to the output side of a specified gate in the first gate array via first switching devicetoa second gate arrayfor carrying out rough adjustment of the delay time interval of the input signal; and a control devicethat adjusts the delay time interval of the input signal by adjusting the capacitances connected to the output side of a specified gate in the first gate array and the number of gate stages in the second gate array

Delay adjustment circuit and a clock generating circuit using the same

A semiconductor integrated circuit including a clock signal propagation gate capable of reducing clock signal skew and controlling a clock signal is provided. The clock signal inputted at a clock origin propagates through buffers ( ) to a clock propagation control gate ( ). The two-level clock propagation control gate ( ) includes an inverter at the first level, and a NAND gate at the second level. The clock signal passed through the clock propagation control gate ( ) propagates through buffers ( ) to reach a sequential circuit ( ) at an end point. The NAND gate ( ) at the second level of the clock propagation control gate ( ) includes nMOS transistors ( ) and pMOS transistors ( ). The inverter ( ) at the first level includes a pMOS transistor ( ) and an nMOS transistor ( ).

Clock signal propagation gate and semiconductor integrated circuit including same

The present invention provides a multistage pipeline latch circuit that tolerates the displacement of a clock edge by exploiting the insertion positions of the latch circuits and the clock input timing to the latch circuits. A latch circuit, operating as a two or more stage pipeline, provides an input flip flop circuit to which an input signal is applied, an output flip flop circuit that supplies an output signal, and a latch circuit provided between the input and output flip flop circuits, a clock signal supply means that supplies a common clock signal to the input and output flip flop circuits and the latch circuits, and a circuit insertion position selection means that determines the insertion position of the input and output flip flop circuits and the latch circuits so that the input of the latch circuit is defined at the center of the through period of the latch circuits are provided.

Multistage pipeline latch circuit and manufacturing method for the same

In an adder apparatus, a first logic circuit performs a NOR operation upon a first bit of an n-bit input signal and a control signal to generate a first signal. A second logic circuit performs an OR operation upon the first bit of the n-bit input signal and the control signal to generate a logic OR signal and performs a NAND operation upon the logic OR signal and a second bit of the n-bit input signal to generate a second signal. Each of third logic circuits performs a NAND operation upon an (i&minus;1)th (i&equals;3, 4, . . . , n) bit of the n-bit input signal and i-th bit of the n-bit input signal to generate a third signal. A carry signal generating circuit receives the first, second and third signals to generate &ldquo;n&rdquo; carry signals. A sum generation circuit receives the n-bit input signal, the &ldquo;n&rdquo; carry signals and the control signal to generate an (n&plus;1)-bit output signal and includes a fourth logic circuit for performing an exclusive NOR operation upon the first bit of the n-bit input signal and the control signal to generate a first bit of the (n&plus;1)-bit output signal.

Growing community of inventors

Tokyo, Japan

Atsushi Yoshikawa