Panasonic Intellectual Property Management Co., Ltd.

Panasonic Corporation

Sumitomo Electric Industries, Limited

Ono Pharmaceutical Co., Ltd.

Daido Steel Co., Ltd.

Kirin Beer Kabushiki Kaisha

Atsushi Yoshida

Takao Yamaguchi

Michael G Yang

Tomoki Ishii

Satoru Tokutsu

Katsuji Aoki

Shouichi Araki

Yuuki Soga

Shoichi Araki

Hiroshi Kutsumi

Nobuyuki Ichiguchi

Kenji Miyazaki

Yosuke Tajika

Wei Zhang

Shinichi Kitamura

Satoshi Matsuura

Takashi Yamada

Shingo Yamamoto

Shinichiro Yahagi

Takanobu Saito

Naoki Inoue

Masakuni Kurono

Kento Tamura

Yasuo Hirooka

Yoshiyuki Kitamura

Kenji Takahashi

Shingo Hotta

Shohei Mori

Ryosuke Misu

Ryuichi Hyakutake

Nozomu Nagashima

Junichiro Mori

Noboru Hibi

Yuuichiro Sakai

Masamitsu Mizuki

Hirotaka Yoshinaga

Shin-ichiro Yahagi

Akio Watanabe

Ning Li

Masaki Hiromoto

A drug is provided, which containing, as an active ingredient, a compound having ABHD6 inhibitory activity in prevention and/or treatment of a disease associated with ABHD6. A compound of formula (I-A) or a pharmaceutically acceptable salt thereof has ABHD6 inhibitory activity and therefore is useful as a pharmaceutical ingredient having potent ABHD6 inhibitory activity in the prevention and/or treatment of a disease associated with ABHD6: in which all symbols represent the same meaning as the symbols described in the specification.

Substituted cyclopenta[c]pyrroles as ABHD6 antagonists

The present invention relates to a Brk inhibitory compound represented by general formula (I) (wherein, all symbols represent the same meanings as the symbols set forth in the specification), a salt thereof, an N-oxide thereof, a solvate thereof, or a prodrug of any of these. 

BRK inhibitory compound

A system includes: a storage that stores a degree of deterioration determined from information that, for each part of each of air-conditioning facilities and/or refrigeration facilities during past inspections, an inspection worker perceived from the part; a first determiner that corrects and determines, on the basis of a history of degrees of deterioration of each part of the air-conditioning facilities and/or the refrigeration facilities during the past inspections, at least either scheduled dates of inspection of the air-conditioning facilities and/or the refrigeration facilities, or a priority of inspection work that is performed on each part of an air-conditioning facility and/or a cooling facility to be inspected; and a controller that causes an indicator to display at least either information indicating the scheduled dates of inspection or information indicating the priority of inspection work as determined by the first determiner.

Inspection management system and inspection management method

A degradation estimation method includes: a service record acquiring step acquiring a service record of maintenance of a device; an analysis step analyzing a degradation state of the device from the service record; a determination standard adjustment step adjusting a first determination standard to a second determination standard depending on the analyzed degradation state, the first determination standard being determined in advance for estimating whether there is degradation of the device or not; a device data acquisition step acquiring first device data indicating state of the device; and a first degradation estimation step estimating whether there is degradation of the device or not using the acquired first device data and the second determination standard.

Degradation estimation method and degradation estimation apparatus

A bus control device () includes a storage () that stores a transmission order of data pieces transmitted from a first node () to each second node (); a sorter () that receives data pieces transferred from each second node toward the first node and refers to a predefined sorting rule to determine a sorting destination of each data piece; a buffer () that stores the sorted data pieces while classifying the sorted data pieces by the second node as a transmission source; and a connection controller () that refers to change permission/rejection information indicating whether or not an order is permitted to be changed while the data piece is transferred from each second node to the first node, and transmits data pieces, the order of which is not changed, from the buffer to the first node in the same order as the transmission order stored on the storage.

Bus control device, relay device, and bus system

An exemplary interface apparatus includes: a header generator which receives, in a first order, a plurality of request headers extracted from a plurality of request packets, generates response headers associated with the request headers, and then stores the response headers so that the response headers are read in the first order; and a header order controller which controls the header generator so that if the plurality of request data have been transmitted to the memory in a second order, the respective response headers are read in the second order.

Interface apparatus and memory bus system

An apparatus state estimation method includes: storing first apparatus data that indicates a state of an apparatus; storing a work record, the work record being a record indicating a work that has been carried out for maintenance of the apparatus; estimating a category that is a malfunction of the apparatus or a content of a measure by using the work record; and learning a relationship between the estimated category and the first apparatus data.

Apparatus state estimation method, apparatus state estimation device, and data providing device

In the bus system, bus interface apparatuses and routers are connected together through packet exchange buses which have been established on the integrated circuit. The bus interface apparatuses are respectively connected to transmission nodes which transmit data of mutually different numbers of bits in one cycle of operation of the bus system. Each of the bus interface apparatuses generates and transmits a packet based on data received from the transmission node connected and header information including size information indicating the number of bits with respect to the transmission node connected. The router analyzes the packet, gets the size information from the header information, determines how to allocate a space in the buffer for storage by reference to the size information gotten, and stores the received packet in the buffer.

Bus interface apparatus, router, and bus system including them

A bus system () for a semiconductor circuit transmits data on a networked bus between a first node and at least one second node via a relay device () arranged on the bus. The bus system () includes a first bus of a low delay and a second bus of a high delay. The first node generates a plurality of packets by attaching, to the data stored in a buffer (), information specifying a priority of transmission. The relay device () converts a priority based on a priority conversion rule, which is determined based on a transmission delay of the high-delay bus, allocates a buffer of a destination relay device to which each packet is to be sent, based on the converted priority, and sends packets in a descending order. The relay device () stores packets in a buffer () based on the priority.

Bus system and computer program

A communication device includes: a receiving terminal; a storage device which stores a rule in which a condition regarding a bus system operation environment and an error tolerance scheme are associated with each other, and information regarding a path length; an error processor which determines the error tolerance scheme by utilizing the condition regarding the bus system operation environment and the rule so as to generate error tolerance information corresponding to the received data according to the determined error tolerance scheme; and a sending terminal for sending at least one packet including the error tolerance information and the data to the bus. The operation environment-related condition is a condition for granting an error tolerance for a transmission path of which a bus path length to another communication device, which is a destination of the data, is greater than a predetermined value.

Communication device, router having communication device, bus system, and circuit board of semiconductor circuit having bus system

An exemplary interface apparatus according to the present disclosure connects together an initiator and a packet exchange type bus network formed on the integrated circuit. In the bus network, if the initiator has submitted request data with a deadline time specified, the initiator receives, by the deadline time, response data to be issued by a node in response to the request data. The interface apparatus includes: a correcting circuit which corrects the deadline time of the request data according to the timing when the request data has been submitted, thereby generating corrected deadline time information; a header generator which generates a packet header that stores the corrected deadline time information; and a packetizing processor which generates a request packet based on the request data and the packet header.

In a bus control system for a semiconductor circuit, data is transmitted between first and second nodes over a network of buses. The bus controller is connected directly to the first node and includes: a route load detector which detects loads on routes that form at least one of a group of forward routes leading from the first to the second node and a group of backward routes leading from the second to the first node; a candidate route extraction circuit which extracts a candidate route from the group of routes so that loads on the routes that form the group become uniform; a route determining circuit which determines the route to transmit the data based on the candidate route and a predetermined selection rule; and a data communication circuit which transmits the data between the first and second nodes based on header information including route information indicating the route.

Bus controller, bus control system and network interface

The access controller conducts arbitration between first nodes, each of which is attempting to transmit data to any of second nodes as destinations through a network of buses. The access controller includes: a buffer which receives the data that have been provided by the first nodes with mutually different required qualities and destinations, classifies the data according to their destinations and required qualities, and stores the classified data separately; an inter-class arbitrator which sequentially selects one of the required qualities of the data after another in the order of their severity; an inter-destination arbitrator which selects the destinations of the data to be transmitted and gets the transmission quantities of the data distributed among the destinations; and a transmission controller which controls transmission of the data based on the required qualities selected by the inter-class arbitrator and the destinations selected by the inter-destination arbitrator.

Access controller, router, access controlling method, and computer program

A router includes a buffer selection section for receiving a flit from an adjacent router and determining whether to store the flit on an input buffer or to store the flit on a bypass buffer. The buffer selection section executes at least one of a first control of, when a bypass process was performed, changing at least one of a transmission path and a transmission flow rate of data based on a transmission state of the router; and a second control of, when a bypass control section did not execute the bypass process, changing at least one of a transmission path and a transmission flow rate of data based on a transmission state of another first router at which data not subjected to the bypass process and data subjected to the bypass process by another second router are joined together.

Router, method for controlling router, and program

Growing community of inventors

Osaka, Japan

Atsushi Yoshida