Sanyo Electric Co., Ltd.

Semiconductor Components Industries, LLC

Sanyo Semiconductor Co., Ltd.

Nara Corporation

Institute of Science and Technology Sanyo Electric Co., Ltd.

Atsushi Wada

Kuniyuki Tani

Shigeto Kobayashi

Takeshi Otsuka

Hajime Mizukami

Kouichi Yamada

Yoshitaka Ueda

Mitsuaki Hatakeyama

Takafumi Nakamori

Yoh Takano

Takashi Asano

Hajime Takashima

Noriaki Kojima

Masayuki Koga

Norihiro Nikai

Seiichi Banba

Toru Dan

Shinji Furuichi

Kohji Sakata

Satoru Sekine

Katsuya Kihara

Yasuyuki Kimura

Yugo Nose

Kenichi Kato

Keiichiro Kagawa

Jun Ohta

A power supply detection circuit detects power feeding to a VBUS terminal from the outside. A charger detection circuit detects the kind of charger by monitoring voltages of a DP terminal and a DM terminal. A control unit adjusts timing and instructs the charger detection circuit to start a charger kind detection process after a notification of detection of power feeding is received from the power supply detection circuit.

Method for detecting a type of charger coupled to an input-output circuit and input-output circuit therefor

An identification terminal voltage detecting circuit detects a voltage of an identification terminal. A video switch is inserted into a signal line connecting a video circuit included in an internal circuit and the identification terminal. When a voltage representing that a video cable is connected to a connector is detected, and then a voltage representing that the video cable is terminated with specified impedance is detected, the control unit turns on the video switch.

Input-output circuit

A power supply circuit generates the internal power supply voltage intVCC from a first power supply capable of supplying a first power supply voltage Vand a second power supply capable of supplying a second power supply voltage V, which is lower than the first power supply voltage V. A first transistor TRis provided between the first power supply and an output node, whereas a second transistor TRis provided between the second power supply and the output node. A first supply unit supplies the inverted value of an output voltage of the first power supply or the inverted value of a voltage corresponding to the output voltage of the first power supply, to the gate input of the first transistor TR. A second supply unit supplies the output voltage of the first power supply or the voltage corresponding to the output voltage of the first power supply, to the gate input of the second transistor TR

Power supply circuit

A power supply detection circuit detects power feeding to a VBUS terminal from the outside. A charger detection circuit specifies the kind of charger by detecting the voltages of a DP terminal and a DM terminal. The charger detection circuit detects open, pull-up, pull-down of at least one of the DP terminal and the DM terminal or formation of a short circuit between both the terminals.

A determination circuit includes a first detecting unit that detects whether first and second power-supply terminals are connected based on a voltage at the second power-supply terminal of a coupling unit that includes the second power-supply terminal connectable to the first power-supply terminal of a device including first and second terminals, and third and fourth terminals connectable respectively to the first and the second terminals. The determination circuit also includes a voltage applying unit that applies first and second voltages to the third and fourth terminals respectively, a second detecting unit that detects that the first and the second terminals are connected to the third and the fourth terminals, respectively, and a discrimination unit that discriminates a type of the device based on voltages at the third and the fourth terminals connected to the first and second terminals, respectively.

Determination circuit

A power supply detecting circuit detects feeding of power to a power supply terminal from the outside. A control unit identifies an accessory device connected to the connector based on a detection result acquired by the identification terminal voltage detecting circuit and a detection result acquired by the power supply detecting circuit. The identification terminal voltage detecting circuit can narrow down accessory device candidates based on whether or not there is feeding of power detected by the power supply detecting circuit.

A first voltage dividing circuit is connected between a power feeding line to feed power from an external power supply to an internal circuit, and a fixed potential to divide a voltage of the power feeding line. A first comparator compares a divided voltage, which has been divided by the first voltage dividing circuit, with a reference voltage, and outputs a signal to turn off a power switch inserted into the power feeding line when the divided voltage exceeds the reference voltage. A first transistor is connected between a first node where the divided voltage, which has been divided by the first voltage dividing circuit, is generated, and the fixed potential, and is turned on when the voltage of the first node exceeds a set voltage.

Protection circuit and input/output circuit

A MOS transistor includes a gate electrode formed in a grid pattern, source regions and drain regions each surrounded by the gate electrode, and a source metal wiring connected to the source regions via source contacts and a drain metal wiring connected to the drain regions via drain contacts. The source metal wiring and the drain metal wiring are disposed along one direction of the grid of the gate electrode. Each of the source regions and the drain regions is a rectangular form having its long side along the length direction of each metal wiring. The source metal wiring and the drain metal wiring are each formed in a zigzag manner in the length direction and are respectively connected to the source contacts and the drain contacts.

Semiconductor device

A capacitor array circuit receives a plurality of input signals, generate a single output signal by combining the plurality of input signals, and output the single output signal. A comparator receives the output signal of the capacitor array circuit. A current source, which is disposed between a predetermined fixed voltage source and an output terminal of the switched-capacitor circuit, supplies the current to the output terminal until the output signal of the comparator changes. A plurality of input capacitors in the capacitor array circuit receives a plurality of input signals in parallel with each other. At least one additional regulating capacitor in the capacitor array circuit store the charge to compensate for an offset component caused by the delay in the comparator. The respective output terminals of the plurality of input capacitors and the at least one additional regulating capacitor are combined into one.

Switched-capacitor circuit having a capacitor array circuit, and analog-to-digital converter using said switched-capacitor circuit

A pixel includes a photodiode, an overflow circuit, a first sensing circuit, and a second sensing circuit. The first sensing circuit charges and discharges a cathode capacitance by a photocurrent flowing through a photodiode, and amplifies an obtained voltage by a source follower amplifier so as to be outputted to a data line. The second sensing circuit charges and discharged the cathode capacitance by the photocurrent flowing through the photodiode, and outputs electric charge stored in the cathode capacitance via the data line. A pixel circuit is configured so that a first mode in which the first sensing circuit becomes active and a second mode in which the second sensing circuit becomes active can be switched. The first mode and the second mode are switched according to an amount of light received by the photodiode included in each pixel circuit. Gain is controlled according to the amount of light received, in the first mode, and the storage time is controlled in the second mode.

Photo detection device

The object is to provide a delay circuit capable of improving the accuracy of delay time with a simple circuit configuration. A delay circuit includes a first delay unit including a plurality of delay elements connected in series for detecting delay time characteristics of the first delay unit, a detection unit detects the number of delay elements used in the first delay unit to delay an input signal by a reference time, a second delay unit including a plurality of delay elements connected in series so as to output a signal delayed in accordance with the delay time characteristics of the first delay unit, and a selection unit selects the number of delay elements in the second delay unit to delay the input signal in accordance with the number of delay elements detected by the detection unit. The ratio between each of the delay values of the plurality of delay elements in the first delay unit and each of the delay values of the corresponding the plurality of delay elements in the second delay unit are equivalent to the ratio between the reference time and a desired delay time in the second delay unit.

Delay circuit

A sub-A-D converter circuit converts a sampled analog signal into a digital signal of a predetermined number of bits. a D-A converter circuit converts the digital signal converted by the sub-A-D converter circuit into an analog signal to generate a residual signal to be processed by a subsequent conversion processing where the analog signal is to be removed from an analog signal to be sampled by the sub-A-D converter circuit. The D-A converter circuit is of a capacitor array type, and an offset compensation voltage used to compensate for at least part of an offset voltage added to the analog signal sampled by the sub-A-D converter circuit is supplied to at least one capacitor in the capacitor array.

Analog-to-digital converter for converting input analog signal into digital signal through multiple conversion processings

In a photo detecting apparatus, a first capacitance is caused by a photo detecting element and the first capacitance is charged or discharged by current flowing through the photo detecting element. A second capacitance is connected in parallel with the photo detecting element, and the second capacitance charges or discharges an electric charge overflowing from the first capacitance. A current control element is connected to a terminal of the second capacitance on a side where the electric charge flows in, and the current control element delivers a current to cancel part of an electric charge when the electric charge overflowing from the first capacitance is stored in the second capacitance.

Photo detecting apparatus comprising a current control element

A plurality of flip-flop circuits, having different circuit configurations, which perform an identical digital signal processing are mixed on a single semiconductor substrate. A first flip-flop circuit among the plurality of flip-flop circuits receives a clock signal supplied from outside the flip-flop circuits, through at least two stage inverters, and operates with clock signals outputted from the inverters. A second flip-flop circuit receives the clock signal supplied from outside the flip-flop circuits through at least one inverter having a less number of stages than the number of stages of the inverter contained in the first flip-flop circuit, and operates with at least one of the clock signal and a clock signal outputted from the inverter.

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Ogaki, Japan

Atsushi Wada