Matsushita Electric Industrial Co., Ltd.

Matsushita Electric Ind., Ltd.

Atsushi Ubukata

Makoto Serizawa

Akihiko Otani

Katsuji Aoki

Shinya Miyaji

Akihiko Ohtani

Masahiro Gion

Tsutomu Mikami

Yoshifumi Matsumoto

Hisato Yoshida

Takio Yamashita

Motohide Nishibata

Akira Sota

Kouichirou Miyawaki

A semiconductor integrated circuit device includes: a first semiconductor chip including a CPU and a debug basic circuit section for verifying operation of a program executed by the CPU; and a second semiconductor chip retained over a principal surface of the first semiconductor chip and including a debug extension circuit section electrically connected to the CPU and the debug basic circuit section. The debug basic circuit section includes a debug command analyzing section for analyzing a command input from outside. The debug extension circuit section formed in the second semiconductor chip includes a debugging function circuit section including at least one debug circuit.

Semiconductor integrated circuit device and debugger device for the same

The present invention provides a debug apparatus that can set complex break conditions, minimize a time lag from the detection of a break event to the break an execution of a program, and has a debug function with a necessary minimized break determinator included in a chip. A part of the break conditions in a sequence is set in an external break determinator. The remaining condition other than the part of the conditions is set in an internal break determinator. While monitoring an operation status of a processor executing a program, when the conditions set in the external break determinator are satisfied, a break enable signal is input to an AND logic circuit via a break enable input terminal and is held. When the break determinator detects the satisfaction of the remaining condition stored in the internal break determinator, a break signal is supplied from the AND logic circuit to the CPU, thereby breaking the program without delay.

Debug apparatus

There is provided a correlation degree operation apparatus in which the search area is readily extensible, in which a high-speed process can be assured even though the search area is extended, and which can be formed in a simple arrangement. The search area memory stores the picture element data of a search area including ((m.times.M).times.L) candidate blocks. The correlation degree operation unit executes an operation of a degree of correlation between a reference picture block and each of the candidate blocks, with the use of picture element data supplied from the search area memory, this operation being executed by a pipeline process for each candidate block group composed of (M.times.L) candidate blocks. The search area memory has the function of supplying four picture element data at the same clock cycle. This enables the correlation degree operation unit to continuously execute the pipeline processes for the candidate block groups. It is therefore possible to continuously execute the operations of correlation degree between the reference picture block having (M.times.N) picture elements and ((m.times.M).times.L) candidate blocks.

Correlation degree operation apparatus, parallel correlation degree

The address generation unit 166 generates a write address for each picture data to be written in the frame memory 169. The memory control unit 165 writes picture data which have the same Y address and consecutive X addresses to the first bank and the second bank alternately per one-page mode length, and further writes picture data which have the same X address and adjacent Y addresses to the different banks. The memory control unit 165 determines a minimum area which consists of an odd number of page mode lengths and includes picture data of a square area having the same Y address, and reads the determined area from the two storage areas alternately per Y address.

Motion vector detection circuit provided with the picture data memory

Picture data memory with high access efficiency in detecting motion

Growing community of inventors

Kyoto, Japan

Atsushi Ubukata