Nippon Electric Co., Ltd.

Atsushi Tomozawa

Rikio Maruta

Yasuo Itoh

Kunihiko Niwa

Shinichi Aikoh

A compandor converts a linear code signal consisting of a polarity bit and a plurality of absolute value bits. The polarity bit represents the polarity of each sample value of an original analog signal. The absolute value bits represent the absolute value of the sample. The compandor converts the linear code into a nonlinear code including the polarity bit, a plurality of segment bits representing the segments in a characteristic curve to which the original analog signal belongs, and mantissa bits which indicate the position of the sample value in that segment. The compandor comprises: a plurality of input terminals for receiving the linear code signal; a first read-only memory means, addressed by a first bit group among the absolute value bits for memorizing a segment bit decision rule; a second read-only memory means, addressed by a second bit group consisting of another plurality of bits among the absolute value bits and some bits in common with the first bit group for memorizing a first mantissa bit decision rule; a third read-only memory means, addressed by the first bit group, for memorizing a second mantissa bit decision rule; and means for selecting the second or third read-only memory means depending on the value of the most significant bit among the segment bits applied from the first read-only memory means.

Digital compandor having nonlinear companding characteristics

A compandor converts a linear code signal consisting of a polarity bit and a plurality of absolute value bits. The polarity bit represents the polarity of each sample value of an original analog signal. The absolute value bits represent the absolute value of the sample. The compandor converts the linear code into a nonlinear code including the polarity bit, a plurality of segment bits representing the segments in a characteristic curve to which the original analog signal belongs, and mantissa bits which indicate the position of the sample value in that segment. The compandor comprises: a plurality of input terminals for receiving the linear code signal; a first read-only memory means, addressed by a first bit group among the absolute value bits for memorizing a segment bit decision rule; a second read-only memory means, addressed by a second bit group consisting of another plurality of bits among the absolute value bits and some bits in common with the first bit group for memorizing a first mantissa bit decision rule; a third read-only memory means, addressed by the first bit group, for memorizing a second mantissa bit decision rule; and means for selecting the second or third read-only memory means depending on the value of the most significant bit among the segment bits supplied from the first read-only memory means.

In a digital time division multiplexed telephone transmission system, a plurality of telephone signals are cyclically sampled and quantized so that each sampled value may be encoded into a binary codeword of a preset number of bits and that a series of codewords equal in number to the telephone signals may constitute a frame and a series of a predetermined number frames may in turn constitute a superframe. At the transmission end, an input circuit (202) receives the time division multiplexed telephone signals, and a code converter (204) coupled to the input circuit and responsive to a state-representing signal successively converts each of the binary codewords into a plurality of modified codewords. The modified codewords are variably assigned comparatively smaller and greater numbers of binary digits depending on the state-representing signal, the comparatively greater number being equal to or smaller than the preset number. A selection circuit (207) is supplied with the modified codewords and selectively allows one of the modified codewords to pass. A bit-number-assigning circuit (205) is coupled to the code converter and responsive to the output of the selection circuit to produce the state-representing signal in response to the corresponding one of at least one preceding frame, and for each of the modified codewords, the bit-number-assigning circuit produces a bit-number-representing signal indicating the number of bits assigned to the binary codeword being transmitted. A multiplexer (206) is coupled to the bit-number-assigning circuit and arranges in time domain the output of the selection circuit, bit-number-representing signal and a superframe synchronization signal. At the reception end, a code-inverse converter (1003) is responsive to the bit-number-representing signal to reproduce the binary codewords from the modified codewords.

Time division multiplexed transmission systems for telephone or like

An asynchronous PCM common decoding apparatus decodes asynchronous PCM signals sent from a plurality of transmitter sources. The apparatus includes a plurality of receiver units each of which generate a digital signal to be decoded, a channel-number-designating signal, and a decode-requesting signal. One or more decoders are provided to decode the digital signals from the receiver units to analog signals. The decoders produce status signals indicating availabilities of the decoders for decoding the digital signals. A common control unit is responsive to both the decode-requesting signals and the status signals to successively allot a combination of a given receiver and a given decoder.

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Tokyo, Japan

Atsushi Tomozawa