Hitachi, Ltd.

Other

Hitachi Software Engineering Company, Ltd.

Hitachi Video and Information System, Inc.

Atsushi Tanaka

Akira Fujibayashi

Kazuhisa Fujimoto

Nobuyuki Minowa

Hiroki Kanai

Hikari Mikami

Hisashi Nanao

Makoto Asari

A disk array controller which includes a channel interface unit for connecting a host computer through a first type channel, a channel interface unit for connecting a host computer through a second type channel, a plurality of disk interface units provided with an interface with a magnetic disk unit respectively, a cache memory unit, and a shared memory unit. The number of access paths connected to said cache memory unit is less than the number of access paths connected to the shared memory unit.

Disk array control device with an internal connection system for efficient data transfer

A disk array control device which includes a plurality of channel interface (IF) units, a plurality of disk IF units, a cache memory unit, and a shared memory unit. The connection system between the plurality of channel IF units and plurality of disk IF units and the cache memory unit is different from the connection system between the plurality of channel IF units and plurality of disk IF units and the shared memory unit. In the invention the plurality of channel IF units and the plurality of disk IF units are connected via a selector to the cache memory unit whereas the plurality of channel IF units and the plurality of disk IF units are directly connected to the shared memory unit with no selectors.

Disk array control device with two different internal connection systems

A disk array controller connected in a star configuration with a plurality of interfaces each having a processor, a shared memory connected to the interfaces by access paths and a common bus connected to the interfaces. The shared memory transmits interruption signals to the interface by way of control signals when one of the processors writes broadcast data into the shared memory.

Broadcast system in disk array controller

A disk array controller which includes a channel interface unit for connecting a host computer through a first type channel, a channel interface unit for connecting a host computer through a second type channel, a plurality of disk interface unit provided with an interface with a magnetic disk unit respectively, a cache memory unit, and a shared memory unit. The number of access paths connected to said cache memory unit is less than the number of access paths connected to the shared memory unit.

A disk array controller, comprising a channel interface unit for connecting a host computer through a first type channel; a channel interface unit for connecting a host computer through a second type channel; a plurality of disk interface units provided with an interface with a magnetic disk unit respectively; a cache memory unit; and a shared memory unit, wherein the number of access paths connected to said cache memory unit is less than the number of access paths connected to said shared memory unit.

A disk array control device includes a plurality of channel interface (IF) units, a plurality of disk IF units, a cache memory unit, and a shared memory unit. The connection system between the plurality of channel IF units and plurality of disk IF units and the cache memory unit is different from the connection system between the plurality of channel IF units and plurality of disk IF units and the shared memory unit. In the invention, the plurality of channel IF units and the plurality of disk IF units are connected via a selector to the cache memory unit whereas the plurality of channel IF units and the plurality of disk IF units are directly connected to the shared memory unit with no selectors.

A disk controller which includes a plurality of interfaces to host computers or disk devices, each interface having a processor, a memory unit coupled to the interfaces in a one-to-one ratio by respective access paths, the memory unit having a memory in which information is stored, and a common bus coupling to the processors included in the interfaces. Each processor of each interface transmits broadcast data to all of the processors of the interfaces, except its own, by way of the common bus.

The disk array controller includes a plurality of interfaces with respective processors for connecting with a host computer or disk devices, duplicated shared memories connected in a one to one ratio between each interface and respective access paths, a selector connected to the plurality of interfaces, and a cache memory connected to the selector. The number of access paths between the selector and the plurality of interfaces is greater than the number of access paths between the cache memory and the selector. Each processor performs dual writing in the duplicated shared memories.

Disk array controller including a plurality of access paths

A disk array controller, comprising a channel interface unit for connecting a host computer through a first type channel; a channel interface unit for connecting a host computer through a second type channel; a plurality of disk interface units provided with an interface with a magnetic disk unit respectively; a cache memory unit; and a shared memory unit; wherein the number of access paths connected to said cache memory unit is less than the number of access paths connected to said shared memory unit.

Duplicated shared memory controller for disk array

A disk array control device which includes a plurality of channel interface (IF) units, a plurality of disk IF units, a cache memory unit, and a shared memory unit. The connection system between the plurality of channel IF units and plurality of disk IF units and the cache memory unit is different from the connection system between the plurality of channel IF units and plurality of disk IF units and the shared memory unit. In the invention the plurality of channel IF units and the plurality of disk IF units are connected via a selector to the cache memory unit, whereas the plurality of channel IF units and the plurality of disk IF units are directly connected to the shared memory unit with no selectors.

Growing community of inventors

Urawa, Japan

Atsushi Tanaka