Kabushiki Kaisha Toshiba

Kioxia Corporation

Tokyo Electric Co.

Atsushi Takayama

Kenji Sakaue

Tatsuyuki Ishikawa

Yoshihisa Kondo

Kosuke Morinaga

Kazuo Toda

Susumu Tanioka

Keisuke Ihara

Takahiro Fujiki

Naoki Wada

Edward Bandy Samigat

Ryo Nogami

Yutaka Tango

Shoji Hoshino

Akiyosi Sasaki

A semiconductor device of an embodiment includes an ECC decoding processing circuit configured to perform ECC decoding on ECC frame data in a lateral direction of a product code frame, an RS decoding processing circuit configured to perform Reed-Solomon (RS) decoding on second frame data in a longitudinal direction of the product code frame, a memory Min which a syndrome generated for the ECC frame data decoded is stored, a memory Min which an RS syndrome generated for ECC frame data for which the ECC decoding has been successful is stored, and a memory D in which ECC frame data for which the ECC decoding has been failed is stored as frame data which cannot be corrected through decoding, and frame collection processing, and iterative correction processing of performing RS decoding on the uncorrected frame data collected in the frame collection processing are executed.

Semiconductor device and semiconductor storage device

According to one embodiment, a storage device includes a storage medium, a DLL circuit, a latch circuit, and a delay amount adjustment circuit. The DLL circuit gives a predetermined amount of delay to an inputted clock signal, the latch circuit latches data outputted from the storage medium in accordance with the clock signal delayed in the DLL circuit, the delay amount adjustment circuit adjusts the delay amount that the DLL circuit is to give to the clock signal based on a latch result by the latch circuit.

Storage device and data latch timing adjustment method

A memory controller including a buffer configured to perform decoding frame-unit data decoded by an LDPC decoder through partial parallel processing based on a check matrix made up of a block of a unit matrix and a plurality of blocks in which each row of the unit matrix is sequentially shifted and store threshold decision information of the data read from a memory section, an LLR conversion section configured to convert the threshold decision information to an LLR, an LMEM configured to store probability information &#x3b2; calculated during iteration processing that repeatedly performs column processing and row processing based on the LLR in an iteration unit equal to or smaller than a size of the block, and a CPU core configured to transfer the probability information &#x3b2; stored in the LMEM to the buffer every time the iteration processing in the iteration unit is completed.

Memory controller, semiconductor memory apparatus and decoding method

Apparatus for separating the juice and pulp of fruit or vegetable material comprises a base incorporating a drive mechanism, a case attached to the base and having a conical bore with the axis thereof extending horizontally between end walls of the case, a rotary member rotatably mounted in the case and driven by the drive member, the rotary member comprising a cutting blade portion and a pressing portion. The case is provided on its upper side near the wide end of the bore with a material inlet opening, on its lower side with a liquid outlet opening having a filter therein, and on a lateral side near the narrow end of the bore with a residual solids outlet opening. The cutting blade portion is spiral and has portion disposed near and confronting the material inlet opening. The pressing portion is conical (but oppositely disposed to the conical bore) and has portions disposed near and confronting both the liquid outlet opening and the residual solids discharge opening.

Apparatus for separating liquid and residual solids

Growing community of inventors

Yokohama, Japan

Atsushi Takayama