Oki Electric Industry Co., Ltd.

Lapis Semiconductor Co., Ltd.

Powerchip Technology Corporation

Atsushi Takasugi

Shigemi Yoshioka

Takeshi Gotoh

Terumi Hiraoka

A memory control circuitcontrols an operation of reading stored data from a memory cellconnected to a word line WL and a bit line BL based on an address Address including a row address Ax and a column address Ay. When the address Address includes redundancy addresses Pto Pdesignating a word line WLa or a bit line BLc connected to a specific memory cell Cc, redundancy decoders-to-replace the specific memory cell Cc with a redundancy memory cell RCc connected to redundancy word lines RWLand RWLor redundancy bit lines RBLand RBL. Redundancy address latch circuits-to-respectively hold the redundancy addresses Pto P, and erase the held redundancy addresses Pto Pbased on a reset signal RS inputted from the memory control circuit

Semiconductor memory apparatus and semiconductor integrated circuit apparatus

An image processing system is provided. A region specifying component specifies one or more playing regions for generating predetermined sounds in an image represented by the moving image data that have been acquired by the acquiring component. A detecting component detects a specific image showing a specific subject existing in the image represented by the moving image data that have been acquired by the acquiring component. An assigning component assigns, for each of the playing regions that have been specified by the region specifying component, sounds to be outputted in a case where the specific image that has been detected by the detecting component overlaps those playing regions. A signal outputting component outputs signals representing the sounds that have been assigned to those playing regions by the assigning component, in a case where the specific image overlaps the playing regions.

Image processing system for outputting signals when an image of a specific object overlaps playing regions, and storage medium in which an image processing program is stored

A method of accessing matrix data of a semiconductor memory having memory banks. The memory banks each having memory cells arranged in X and Y directions, a Y decoder for selecting Y-direction addresses of the memory cells and an X decoder for selecting X-direction addresses of the memory cells, predicated on the memory banks being operable independently. Items of data specified by a specified number of continuous X addresses and having the same Y addresses are successively written into or read from the memory cells arranged in the X direction, which are specified by X addresses corresponding to 1+knth in one of the banks. After all data have been written into or read from the specified memory cells, corresponding data are successively written into or read from the memory cells specified by X addresses corresponding to 2+knth in another one of the banks.

Method of accessing matrix data with address translation circuit that enables quick serial access in row or column directions

In a semiconductor memory, memory banks each having memory cells are arranged in X and Y directions. Each of the memory banks include a Y decoder for selecting Y-direction addresses of the memory cells and an X decoder for selecting X-direction addresses of the memory cells, predicated on a memory having memory banks operable independent from one another. Items of data specified by a specified number of continuous X addresses and having the same Y addresses are successively written into or read from the memory cells arranged in the X direction, which are specified by X addresses corresponding to 1&plus;knth (where k&equals;0, 1, 2 . . . ) in one of the banks. After all the data have been written into or read from the specified memory cells, the corresponding data are successively written into or read from the memory cells specified by X addresses corresponding to 2&plus;knth in another one of the banks.

Semiconductor circuit with address translation circuit that enables quick serial access in row or column directions

A serial access memory having a first memory cell array and a second memory cell array. The serial access memory is provided with a control circuit for controlling the Most Significant Bit (MSB) of an address supplied to each of the first and second memory cell arrays. The control circuit causes the operations of circuits in the first memory cell array to become identical to those of circuits in the second memory cell array, thereby making it possible to read data at a high speed. An STN type LCD including the serial access memory, has a display device that facilitates production of memory maps in the memory cells without a need for externally-mounted elements such as a multiplexer.

Serial access memory

In a semiconductor memory, memory banks each having memory cells are arranged in X and Y directions. Each of the memory banks include a Y decoder for selecting Y-direction addresses of the memory cells and an X decoder for selecting X-direction addresses of the memory cells, predicated on a memory having memory banks operable independent from one another. Items of data specified by a specified number of continuous X addresses and having the same Y addresses are successively written into or read from the memory cells arranged in the X direction, which are specified by X addresses corresponding to 1&plus;knth (where k&equals;0, 1, 2, . . . ) in one of the banks. After all the data have been written into or read from the specified memory cells, the corresponding data are successively written into or read from the memory cells specified by X addresses corresponding to 2&plus;knth in another one of the banks.

A serial access memory reduces a chip size and saves a process development. The serial access memory has first decoders that output first selection signals in response to a received address signal, write registers for temporarily storing data, a first switch that is connected between the write data buses and the write registers and provides conduction between the write data buses and the write registers in response to the first selection signals, a memory array having memory cells and a plurality of memory columns wherein the memory cells are connected through word lines, and a second switch that is connected between the write registers and the memory columns and provides conduction between the write registers and the memory columns in response to second selection signals, wherein the write registers are connected to a predetermined number of the memory columns, and the second switch provides conduction between the write registers and only one of the present invention number of the memory columns in response to the second selection signals.

Serial access memory having data registers shared in units of a plurality of columns

A semiconductor memory circuit comprises a memory array including an X decoder and column units. Each of the column units has a Y decoder, memory cells and bit line pairs. The semiconductor memory circuit further comprises switching circuits each having an input connected to one of the Y decoders and outputs. The switching circuit is connected to the input and one of the outputs in response to a control signal. The semiconductor memory circuit further comprises buffers each of which is connected to one of the outputs of the switching circuits, ports each of which is connected to one of the buffers and a memory control signal generating circuit outputting the X address and Y address.

Semiconductor memory circuit in which pattern widths of switching

Video camera system and semiconductor image memory circuit applied to it

Memory device

According to a first aspect of the invention, a memory device has a main memory array and a sub memory array. In a single burst, data are read from a series of columns in the main memory array, transferred from one column in the main memory array to one column in the sub memory array, read from a series of columns in the sub memory array, and written into the above-mentioned one column in the main memory array. According to a second aspect of the invention, a memory device has a memory array and separate external data input terminals and output terminals. In a single burst, data are read from a series of columns in the memory array, and written to one of the columns, preferably the last column in the series. Input of the written data is preferably simultaneous with the output of the data read from the column to which the input data are written.

Memory device providing burst read access and write access from a single

A serial access memory includes a data transfer unit including a memory cell array having a plurality of memory cells arranged therein for storing data therein, a first transfer register electrically connected to the memory cell array through a first switching circuit and a second transfer register electrically connected to the first transfer register through a second switching circuit. The data transfer unit is provided so that when each of the first and second switching circuits is in an ON state, data passes through the first transfer register so as to be transferred from the memory cell array to the second transfer register and when the first switching circuit is in an ON state and the second switching circuit is in an OFF state, data is transferred from the memory cell array to the first transfer register.

A semiconductor memory device of the invention includes memory cells each having a transistor and a capacitor, bit lines electrically connected to the memory cells, data lines, transfer circuits each electrically connecting the bit lines and the data lines in response to column selection signals, and conductive lines each electrically connected between a transistor and a capacitor of selected ones of the memory cells and having a predetermined potential. Owing to this arrangement, the semiconductor memory device can be realized wherein volatile memory cells and non-volatile memory cells are provided within a single memory cell array. Further, the semiconductor memory device of the invention is of a semiconductor memory device having high flexibility, wherein the ratio between the volatile memory cells and the non-volatile memory cells can be easily decided according to a user's demand.

Semiconductor memory device having volatile storage unit and

A semiconductor memory, device of the invention includes memory cells each having a transistor and a capacitor, bit lines electrically connected to the memory cells, data Dines, transfer circuits each electrically connecting the bit lines and the data lines in response to column selection signals, and conductive lines each electrically connected between a transistor and a capacitor of memory cell selected ones of the and having a predetermined potential. Owing to this arrangement, the semiconductor memory device can be realized wherein volatile memory cells and non-volatile memory cells are provided within a single memory cell array. Further, the semiconductor memory device of the invention is of a semiconductor memory device having high flexibility, wherein the ratio between the volatile memory cells and the non-volatile memory cells can be easily decided according to a user's demand.

Growing community of inventors

Tokyo, Japan

Atsushi Takasugi