Fujitsu Corporation

Kabushiki Kaisha Toshiba

Sumitomo Electric Industries, Limited

Toshiba Storage Device Corporation

Duaxes Corporation

Ishino Gasket Mfg., Co., Ltd.

Atsushi Suzuki

Takeshi Hara

Yukio Abe

Shigenori Yanagi

Toshimasa Namekawa

Shinji Miyano

Tomoyuki Hattori

Yasuo Matsuda

Nobuhiro Akasaka

Mitsuo Kamimura

Kazuhiro Watanabe

Toshifumi Hosoya

Takeshi Ohwe

Hajime Arao

Hiroshi Takekawa

Yoshinari Higashino

Kunihiro Shimada

Kiyoshi Sakuma

Kentaroh Katoh

Takahiro Yamamoto

Hidehiko Kira

Yasuhiro Yoneda

Norio Kainuma

Hiroki Ishikawa

Daisuke Mizutani

Keiichi Hasegawa

Chen Kong Teh

Mitsuaki Tamura

Takayuki Shimazu

Itaru Sakabe

Motoyoshi Kimura

Mitsugu Nagoya

Ryosuke Koishi

Keisuke Okada

Hiroshi Takizawa

Kaoru Okuno

Eiji Sugawara

Toshihisa Yokochi

Michiko Harumoto

Kazumasa Oishi

Hirokazu Yamanishi

Shinji Hiraoka

Tsutomu Chikazawa

Kazunori Tanaka

Noboru Nakama

Kazuya Kobayashi

Hideo Itoh

Fumiya Kudo

Shunji Saitoh

Hideyuki Motoori

Masaki Oyagi

Hisashi Tanji

Seijun Tanikawa

Nobumasa Ohya

Masashi Takada

Masashi Nagashima

Mitsutaka Satou

Ayaka Mori

Ren Ishikawa

Toshiaki Katsumata

Yukitomo Matsumoto

Hideki Muramatsu

Namieki Osawa

Naoyuki Kato

Kenji Yamana

Ryosuke Hirose

An optical module () of the invention includes a circuit substrate () on which light receiving and emitting elements () are mounted, a connector component () for holding optical fibers (), and a lens array component () which is fixed on the circuit substrate () and optically connects the optical fibers () to the light receiving and emitting elements () on the circuit substrate (), and the circuit substrate () has a lens array mounting region (A) in which the lens array component () is fixed and a connector component opposed region (A) opposed to the connector component (), and thermal insulation space is formed between the connector component () and the connector component opposed region (A).

Optical module

According to one embodiment, an A/D converter includes a first delay cell column in which a plurality of delay cells, to which a first bias current corresponding to a difference voltage between an input voltage and a reference voltage is supplied, is connected in series. The converter includes a second delay cell column in which a plurality of delay cells, to which a second bias current corresponding to a negative-phase difference voltage of the difference voltage is supplied, is connected in series. The converter includes an encoder unit configured to encode a difference value, in delay time of signal propagation, between the first delay cell column and the second delay cell column.

A/D converter and semiconductor integrated circuit

A lens component has a element-side lens portionwhich is provided so as to face a light emitting and receiving elementmounted on a circuit substrate, a positioning portionthat protrudes such that the element-side lens portionis separated from the circuit substrateby a predetermined distance, and an adhesion portionthat forms an adhesive-agent filling space S, which is filled with an adhesive agent, between the circuit substrateand the adhesion portion, in a state where the positioning portioncontacts with the circuit substrateand the element-side lens portionis fixed so as to face the light emitting and receiving element

Lens component and optical module provided with the same

A first pump circuit generates a first voltage for decreasing the distance between primary electrodes. The first voltage is limited to a predetermined limit by a first limiter circuit. A second pump circuit generates a second voltage for keeping the distance between the primary electrodes constant. A third pump circuit generates the second voltage and has a supplying capacity smaller than the first one. The second voltage is limited by second and third limiter circuits. A ripple capacitor is charged up to the second voltage by the second pump circuit and the second limiter circuit within a period of time the first voltage is being generated. When a supplying voltage of the first pump circuit reaches to the first voltage, and a deformation stops, the second voltage is supplied by the third pump circuit and the third limiter circuit instead of the second pump circuit and the second limiter circuit.

Semiconductor integrated circuit and method of controlling MEMS-type variable capacitance capacitor

The present invention provides a technique for improving the security of access to contents. A virus/phishing site list contains a list of URLs of phishing sites, which masquerade as valid websites and are provided with an attempt to acquire private information including card numbers, PIN numbers and passwords, from users illegally. When a communication control unit receives, via a network, a packet that contains communication data for requesting access to a content, a search circuit compares the URL of the content to be accessed included in the communication data, with URLs of phishing sites included in the virus/phishing site list. If the address of the content to be accessed matches a URL of a phishing site, a process execution circuit will prohibit the access to the content.

Communication control device and communication control system

A phase detecting circuit includes a latch circuit that switches, based on an OR signal and an AND signal of two clock signals to be subjected to phase comparison, one of outputs used for generation of two pulse signals on an advance phase side and a delay phase side to a preparation operation state for performing the phase comparison and a circuit operation state after the phase comparison, and holds the output in the states.

Phase detecting circuit and PLL circuit

A semiconductor integrated circuit device including a fuse latch circuit including a fuse and a latch circuit for latching fuse data held in the fuse, a fuse counter circuit for counting the number of transfers of the fuse data, and a control circuit including a transmitter circuit for transmitting the fuse data to a memory macro connected to the control circuit, and a detour data path circuit which when the fuse data is not transferred, does not transfer the fuse data to the memory macro, and forms a detour data path for detouring the fuse data in the detour data path circuit itself.

Semiconductor integrated circuit device, redundancy system, and redundancy method for latching and transmitting fuse data

A booster circuit includes a first booster unit configured to boost a power supply voltage to a predetermined voltage value, a transfer gate transistor transferring the voltage received from the first booster unit to an output terminal, a switching transistor connected between an input terminal receiving the voltage from the first booster unit and a gate electrode of the transfer gate transistor, and a second booster unit configured to boost a voltage applied to a gate electrode of the switching transistor. The second booster unit includes an NMOS booster transistor. A drain electrode of the booster transistor is connected to the output terminal, a source terminal of the booster transistor is connected to a terminal to which a boosted voltage is to be applied, and a gate electrode of the booster transistor is connected to a booster capacitor.

Booster circuit

A semiconductor integrated circuit comprises a first transistor which has one end connected to a first node where a first voltage is output, and which transfers the first voltage to an output terminal, a second transistor which has one end connected to a second node where the second voltage is output, and which transfers the second voltage to the output terminal, a third booster circuit which supplies a third voltage obtained by further boosting the first voltage to a control terminal of the first transistor, and a fourth booster circuit which supplies a fourth voltage obtained by further boosting the second voltage to a control terminal of the second transistor. The third booster circuit lowers a voltage supplied to the control terminal of the first transistor to turn off the first transistor at a time after discharging of the first node is started. The fourth booster circuit increases, in accordance with a signal from the third booster circuit, a voltage supplied to the control terminal of the second transistor to turn on the second transistor after the first transistor is turned off.

Semiconductor integrated circuit

A medium-opposed surface of a slider body is hemisected into first and second areas by the centerline extending in the longitudinal direction of the slider body. The second area is designed to generate a positive pressure larger than that generated at the first area when a load acting on the slider body in a direction toward a recording medium decreases. The head slider of the type is allowed to enjoy the imbalance of the lift on the slider body. This imbalance can be utilized to intentionally induce increases in the roll angle and the pitch angle of the slider body. The increase in the roll and pitch angles causes disappearance of the lift and the negative pressure generated at the medium-opposed surface. The head slider can reliably be distanced from the moving surface of the recording medium solely with the assistance of the airflow acting on the medium-opposed surface.

Head slider capable of being reliably released from effect of moving recording medium

A control apparatus detects positional information of a head performing writing processing every predetermined time interval, and computes next-sample projected positional information of the head based on the difference between the positional information detected the previous time and the positional information detected the current time, and the current detected positional information for every position information detected. The control apparatus determines whether the computed next-sample projected positional information is greater than a next-sample projected position threshold which is a predetermined threshold. Following this, in the case that determination is made that the next-sample projected positional information is greater than the projected position threshold, the disk control apparatus controls a storage device to stop the writing processing after the writing processing is performed through the end of the sector wherein the writing processing is currently being performed.

Control apparatus, storage apparatus, and writing control method

When a head is subjected to external vibration while a controller is controlling the head according to a positioning-oriented controller characteristic, the positioning-oriented controller characteristic are changed to a vibration-reducing controller characteristic. Moreover, when the external vibration stop while the controller is controlling the head according to the vibration-reducing controller characteristic, the vibration-reducing controller characteristic are changed to the positioning-oriented controller characteristic.

Controller-characteristic changing apparatus, storage device, controller-characteristic changing method, and computer product

A data storage device executes sector guarantee processing at an unexpected power supply disconnection. The sector guarantee processing can be accurately performed even if the fluctuation of power supply voltage during normal operation is high. The voltage of the power supply is monitored via an A/D converter. The control unit calculates a voltage change value, which is a relative value of the detected voltage of the power supply, and judges power supply disconnection by the level of the voltage change value, to perform sector guarantee processing. The voltage fluctuation during normal operation and the voltage fluctuation at power supply disconnection can be distinguished, power supply disconnection can be accurately detected, and write disable status can be judged.

Data storage device and write processing method for data storage device

Upon obtaining a detection signal of a shock sensor that detects a shock applied to an apparatus for output, a write disabling unit disables writing by a head on a medium over a predetermined time corresponding to a shock convergence. A determining unit determines, during the write disable, whether an output of the shock sensor is a detection output of the shock sensor due to a shock or an erroneous detection output of the shock sensor due to power supply fluctuations. A sensitivity control unit increases a detection sensitivity of the shock sensor when the determining unit determines that the output is a detection output due to the shock, and decreases the detection sensitivity of the shock sensor and clears the write disable when the determining unit determines that the output is an erroneous detection output due to power supply fluctuations.

Storage apparatus, and control method and program

Growing community of inventors

Kawasaki, Japan

Atsushi Suzuki