Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Other

Renesas Electronics Corporation

Hitachi, Ltd.

Atsushi Shiraishi

Hirotaka Nishizawa

Haruji Ishihara

Motoki Kanamori

Kunihiro Katayama

Yosuke Yukawa

Atsushi Shikata

Shigeo Kurakata

Kouichi Kanemoto

Yousuke Yukawa

Hidefumi Oodate

Shinsuke Asari

Chiaki Shinagawa

Yasuhiro Nakamura

Takayuki Tamura

Manabu Inoue

Shigemasa Shiota

Takeshi Suzuki

Chiaki Kumahara

Makoto Obata

Kenzo Matsumura

Yuichiro Onuki

In the initial setting of a memory card, the flash check data FD stored in a flash memoryis read out, this data FD is compared with the operation check data FDstored previously in the ROM, the write check data FDstored in the ROMis written, if a fault is not detected, to the flash memory, and this data is read again and is compared with the write check data. FDof the ROM. When any fault is not detected in comparison of these data, the CPU determines that the flash memoryis normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a registerto set a controllerto the sleep mode. When the command CMD is received during this period, data comparison is executed again.

Memory card and its initial setting method

The service life of memory cards is to be substantially elongated against the occurrence of faulty blocks. A control logic searches blocks in a nonvolatile memory cell array for any acquired fault on the basis of a fault-inviting code in a management information section. If any faulty block is detected, the faulty block will be subjected to write/read comparison of data to judge whether or not the data in the block are normal. Any block determined to be normal will undergo rewriting of its fault-inviting code and registered as a normal block. Further, the registered block is stored into a write management table in the management area as a writable block. This enables an essentially normal block judged faulty on account of an erratic error or some other reason to be restored.

Memory apparatus which provides notification of memory capacity

An IC card has a card substrate having semiconductor integrated circuit chips mounted thereon and a plurality of connector terminals formed thereon. The connector terminals are exposed from a casing. The connector terminals are laid out in plural sequences in staggered form between sequences adjacent to one another forward and backward as viewed in an IC card inserting direction. Owing to the adoption of the staggered layout, a structure or configuration wherein the amounts of protrusions of socket terminals of a card socket are changed and the socket terminals are laid out in tandem, can be adopted with relative ease. If a connector terminal arrangement of a downward or low-order IC card is adopted as a specific connector terminal sequence as it is, whereas a function dedicated for an upward or high-order IC card is assigned to another staggered connector terminal arrangement, then backward compatibility can also be implemented with ease.

IC card

In the initial setting of a memory card, the flash check data FD stored in a flash memoryis read out, this data FD is compared with the operation check data FDstored previously in the ROM, the write check data FDstored in the ROMis written, if a fault is not detected, to the flash memory, and this data is read again and is compared with the write check data. FDof the ROM. When any fault is not detected in comparison of these data, the CPU determines that the flash memoryis normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a registerto set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.

A multifunction IC card (MFC) has compatibility with a multimedia card, an SD card, etc. in that connector terminals (#through #) are disposed on a card substrate () in two rows in a zigzag fashion, and realizes multifunction facilities in that a memory card unit () and an SIM (Subscriber Identity Module) card unit () are respectively connected and mounted to predetermined terminals of the connector terminals (#through #). The memory card unit () and the SIM card unit () are respectively separately provided with areas for storing secret codes for security. Thus, one IC card is capable of implementing multifunction facilities different in security level. Owing to the adoption of a plural-column layout corresponding to a form typified by the zigzag fashion in an array of the connector terminals, a relatively simple structure can be adopted in a card slot.

A risk of data garbling due to cumulative impact of disturbances occurring in memory areas in which no rewrite occurs is to be prevented. A memory device has an erasable and writable nonvolatile memory and a control circuit, wherein the control circuit is enabled to perform processing at a prescribed timing to replace memory areas. The replacement processing is accomplished by writing stored data in a first memory area in which rewriting is relatively infrequent into an unused second memory area, and making the second memory area into which the writing has been done a used area in place of the first memory area. Since this replacement processing is intended to replace memory areas in which rewriting is infrequent with other memory areas as described above, it is possible to prevent the risk of data garbling due to the cumulative impact of disturbances occurring in memory areas in which no rewrite occurs.

Nonvolatile memory wear leveling by data replacement processing

Memory card apparatus configured to provide notification of memory capacity

A multifunction IC card (MFC) has compatibility with a multimedia card, an SD card, etc. in that connector terminals (#through #) are disposed on a card substrate () in two rows in a zigzag fashion, and realizes multifunction facilities in that a memory card unit () and an SIM (Subscriber Identity Module) card unit () are respectively exclusively connected and mounted to predetermined terminals of the connector terminals (#through #). The memory card unit () and the SIM card unit () are respectively separately provided with areas for storing secrete codes for security. Thus, one IC card is capable of implementing multifunction facilities different in security level. Owing to the adoption of a plural-column layout corresponding to a form typified by the zigzag fashion in an array of the connector terminals, a relatively simple structure can be adopted in a card slot, wherein the amounts of protrusion of slot terminals in a card slot are alternately changed in association with a zigzag section, and the slot terminals are disposed in a row in parallel as a whole.

When a non-volatile memory write error occurs in a card storage device containing a non-volatile memory and an error correction circuit, write data is read from the non-volatile memory and a check is made if the error can be corrected by the error correction circuit. If the error can be corrected, the write operation is ended. If the error correction circuit cannot correct the error, substitute processing is performed to write data into some other area.

Non-volatile semiconductor memory device

A memory card is provided with a transfer control circuit, a write control circuit and a judging circuit. The transfer control circuit outputs a transfer flag signal during the data transfer. The write control circuit outputs an internal busy signal during the data write operation. The judging circuit outputs a transfer interruption signal when a card selection signal of the host is negated during the input of the transfer flat signal and also outputs a suspension signal when the card selection signal is negated during the input of the internal busy signal. A CPU invalidates the data being transfer to interrupt the transfer process upon reception of the transfer interruption signal and completes, upon reception of the suspension signal, the process being executed and stays in the waiting condition. Consequently, even when the timing signal not conforming to the standards is transferred, the host can select the optimum processing operation from the internal processing conditions and thereby execute the selected operation.

Non-volatile memory card and transfer interruption means

The present invention is directed to suppress data loss caused by power shut-down during a rewriting process and to shorten time required to make a depletion check. A nonvolatile memory apparatus includes a rewritable nonvolatile memory and a card controller. The nonvolatile memory has a physical address area corresponding to a logical address and a save area. In response to a data rewrite instruction on a required logical address, the card controller stores data in a predetermined physical address area corresponding to the logical address to the save area and rewrites the data stored in the physical address area. When rewriting of the physical address area is incomplete, the card controller rewrites the data in the physical address area with the data stored in the save area. Thus, data loss caused by the power shut-down can be suppressed by data backup, and it is sufficient to make the depletion check in two places of the save area and the physical address area.

Nonvolatile memory apparatus which prevents destruction of write data caused by power shutdown during a writing process

Integrated circuit card having staggered sequences of connector terminals

In the initial setting of a memory card, the flash check data FD stored in a flash memoryis read out, this data FD is compared with the operation check data FDstored previously in the ROM, the write check data FDstored in the ROMis written, if a fault is not detected, to the flash memory, and this data is read again and is compared with the write check data FDof the ROM. When any fault is not detected in comparison of these data, the CPU determines that the flash memoryis normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a registerto set a controllerto the sleep mode. When the command CMD is received during this period, data comparison is executed again.

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Kodaira, Japan

Atsushi Shiraishi