Kabushiki Kaisha Toshiba

Oki Electric Industry Co., Ltd.

Toshiba Electronic Devices & Storage Corporation

Atsushi Shimbo

Koichi Fujisaki

Masahiro Ishiyama

Toshio Okamoto

Yuichi Komano

Atsushi Inoue

Mikio Hashimoto

Yoshikazu Hanatani

Hirofumi Muratani

Tomoko Yonemura

Taichi Isogai

Kenji Ohkuma

Hanae Ikeda

Kenichiro Furuta

Atsushi Fukumoto

Shinichi Kawamura

Yoshiyuki Tsuda

Hiroshi Sukegawa

Taku Kato

Akihiro Kasahara

Hiroyuki Sakamoto

Hideo Shimizu

Toru Kambayashi

Shinichi Matsukawa

Yoshihiko Hirose

Hiromi Aoyagi

Toshinari Takahashi

Ichiro Tomoda

Shinichi Yasuda

Tetsufumi Tanamoto

Osamu Moriya

Jiro Amemiya

Tsukasa Endo

Masao Murota

Shinnosuke Yamaoka

Tatsuya Kishi

Satoshi Watanabe

Takao Marukame

Yuichiro Mitani

Masashi Takada

Takeshi Kawabata

Akira Ikeda

Toshio Kato

Hideyuki Miyake

Yoshihito Shimazaki

Masahiko Motoyama

Ryuiti Koike

Yuuki Tomoeda

Noriko Inoue

Shinji Hayakawa

Kazuo Ohta

Masao Murato

Atsushi Inque

Kyoto Takabayashi

Akira Tomita

Ryusuke Murakami

According to one embodiment, a data protection apparatus includes a processor configured to execute an encryption process on log data including a data frame including a plurality of pieces of data generated along a time sequence. The processor is configured to encrypt each of the pieces of data with a corresponding encryption key among a first initial key and a first encryption keys generated in a forward direction to a time sequence of the pieces of data. The processor is configured to encrypt each of a plurality of pieces of data encrypted with the corresponding encryption key with a corresponding encryption key among a second initial key and a second encryption keys generated in a backward direction to a time sequence of the pieces of data.

Data protection apparatus, electronic apparatus, method, and storage medium

An electronic apparatus includes a controller. The controller includes an instruction executer configured to generate or acquire data, an issuer configured to accept a request and issues a time stamp, a first updater configured to update a first counter value according to a first operation, a second updater configured to update a second counter value in accordance with issuance of the time stamp, a first non-volatile memory to hold the first counter value and a secret key, and a volatile register to hold the second counter value. The time stamp is a message authentication code or a digital signature issued from the first and second counter values and the data. The second counter value is not stored in the first non-volatile memory.

Electronic apparatus for time series data management, and method and storage medium

According to one embodiment, an information processing apparatus is allowed to access a storage device storing time-series data generated by a first device. The information processing apparatus includes a processor holding a first public key and a first private key. The processor is configured to acquire a program for correcting an error in first data on a first product from a first entity. The processor is configured to correct the correction target first data, using data in a predetermined range of the time-series data. The processor is configured to generate ground data indicating correction grounds for the corrected correction target first data, based on the data in the predetermined range, and add the ground data to the corrected correction target first data.

Information processing apparatus, method, and storage medium

A control device of the present embodiment has a communication I/F, a built-in non-volatile memory, a controller, an external-serial-memory I/F, a security management module, and an access controller. The communication I/F enables communication with outside. The built-in non-volatile memory has a first storage region, which stores an initialization program which carries out initialization operation, and a second storage region, which stores currently used firmware which is executed after the initialization operation and acquires firmware for update via the communication I/F. The controller executes the initialization program and the currently used firmware. The external-serial-memory I/F communicably connects the device of its own to an external non-volatile memory via a serial bus. The security-mode management module fixes an access control setting of the built-in non-volatile memory and the external non-volatile memory. The access controller outputs a level signal different from the serial bus.

Control device, information processing device, and information processing system

An information processing device updates its own secret key according to an update request including request order information, the information processing device being provided with: a storage unit that stores, in a nonvolatile manner, a master secret key, a secret key, and order comparison information that enables comparison of the request order of the update request; and an update unit that, in a case where the update request has been made, compares the request order information and the order comparison information, and in a case where it has been determined that the order of the update request is authorized, updates the order comparison information to information corresponding to the request order information before update processing of the secret key is performed by using the master secret key.

Information processing device, information processing system, and method for controlling information processing device including comparing request order information and order comparison information

According to one embodiment, an information processing apparatus is applied to an embedded system in an electric device and includes a first circuit. The first circuit is configured to request a server different from the information processing apparatus to determine whether a debug or software change is possible in response to external access.

Information processing apparatus, system and method

According to one embodiment, a random number generating circuit includes first to N-th oscillating circuits (N is a natural number equal to 2 or greater), first to N-th latch circuits that latch outputs of the first to N-th oscillating circuits by a first clock having a first frequency, first to N-th exclusive OR circuits, (N+1)-th to (2&#xd7;N)-th latch circuits that latch outputs of the first to N-th exclusive OR circuits by the first clock, an (N+1)-th exclusive OR circuit that outputs an exclusive OR of outputs of the (N+1)-th to (2&#xd7;N)-th latch circuits, and an M-bit shift register that converts serial data output from the (N+1)-th exclusive OR circuit into M-bit parallel data (M is a natural number equal to 2 or greater) by a second clock having a second frequency.

Random number generating circuit

According to an embodiment, an authentication device includes an acquiring unit, a predicting unit, and an authenticating unit. The acquiring unit is configured to acquire performance information of a first device that is a device to be authenticated. The predicting unit is configured to predict performance information of a second device that is a device being a reference for authentication according to a change with time from initial performance information. The authenticating unit is configured to perform an authentication process of determining whether or not the first device falls into the second device on a basis of a degree of agreement between the performance information acquired by the acquiring unit and the performance information predicted by the predicting unit.

Authentication device, authentication method, and computer program product

According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an external device, includes: a memory including a special area that is a predetermined data storage area; a key storage unit that stores therein a second key that corresponds to a first key used by the external device to convert the data; a converting unit that receives, from the controller, data to be written into the special area and generates converted data by converting the data to be written using the second key; and a writing unit that writes the converted data into the special area.

Memory device for converting data received from controller controlling reading and writing of data

According to an embodiment, an encryption device performs encryption processing using an encryption key and calculates encrypted data from plain data. The encryption device includes: a register; an input unit configured to receive plain data; a first partial encryption unit configured to calculate first intermediate data from the plain data; a second partial encryption unit configured to calculate (i+1)-th intermediate data based on i-th intermediate data and the encryption key; a first transform unit configured to: transform j-th intermediate data into j-th transformed data; and store the j-th transformed data in the register; and a second transform unit configured to transform the j-th transformed data into the j-th intermediate data; a third partial encryption unit configured to calculate encrypted data from the N-th intermediate data. The second partial encryption unit is configured to repeat processing to calculate (j+1)-th intermediate data while j is equal to from 1 to N&#x2212;1.

Encryption device

Memory chip for converting data received from controller controlling reading and writing of data

According to one embodiment, in a key scheduling device, a non-linear transformation unit non-linearly transforms at least one of partial keys resulting from dividing an expanded key. A first linear transformation unit includes first and second circuits. The second circuit linearly transforms the partial key by directly using a transformation result from the non-linear transformation unit. A first storage stores the partial key linearly transformed by the first linear transformation unit. A second linear transformation unit linearly transforms, inversely to the first linear transformation unit, each of partial keys other than the partial key linearly transformed by the second circuit out of the partial keys stored in the first storage, and outputs inversely transformed partial keys. A second storage stores one of inputs to the second circuit. An outputting unit connects the respective inversely transformed partial keys and the input stored in the second storage to be output as a second key.

Key scheduling device and key scheduling method

An arithmetic device includes an input unit inputting data that are elements of a group; a converting unit is configured, when the input data are in a second representation, to convert the input data into a first representation and to perform arithmetic operation on the converted first representation using an operand in the first representation in which at least one subcomponent is a zero element to convert the converted first representation into first converted data expressed in the first representation, and when the input data are in the first representation, to perform arithmetic operation on the input data using the operand in the first representation in which at least one subcomponent is a zero element to convert the input data into second converted data expressed in the first representation; and an operating unit that performs arithmetic processing on the first or the second converted data using secret information.

Arithmetic device, method, and program product

According to one embodiment, a cryptographic processing apparatus is provided with first to fifth units. The first unit mask-converts input data from first temporary mask into first fixed mask (an invariable value in a first linear operation). In an encryption, the third unit performs a nonlinear operation on the mask-converted data and outputs a first result masked with second fixed mask data (an invariable value in a second linear operation). The fourth unit performs the second linear operation and outputs a encryption result masked with second fixed mask data. In a decryption, the second unit performs the first linear operation on the mask-converted data and outputs a second result masked with the first fixed mask. The third unit performs the nonlinear operation and outputs a decryption result masked with the second fixed mask. In encryption/decryptions, the fifth unit converts the mask of the encryption/decryption results into second temporary mask.

Cryptographic processing apparatus and operation method

Growing community of inventors

Tokyo, Japan

Atsushi Shimbo