Sharp Kabushiki Kaisha Corporation

Atsushi Semi

Yoshihiro Sekimoto

Yasuo Torimaru

Kaneo Kawaishi

A camera moduleof the present invention includes a moving magnet type mechanical shutterand a lens unit(lens drive section) for driving a lens by electromagnetic force. A magnetic field for driving the lens is set so that a light path is closed by a shutter fin while a magnetic field leaked from the lens unitis acting on a drive mechanism of the mechanical shutter. With the configuration, the leak magnetic field leaked from the lens unitcauses the light path to be closed at a faster speed by the shutter fin of the mechanical shutter. Accordingly, generation of a smear can be prevented by the camera module including the lens drive section and the moving magnet type mechanical shutter, which are driven by the electromagnetic force.

Camera module and electronic device including the same

A semiconductor device includes: a semiconductor substrate; a bonding pad having an interconnection region that provides for an external electrical contact; a first interlayer insulating layer interposed between the semiconductor substrate and the bonding pad; and a metal wiring layer that is embedded in the first interlayer insulating layer. The metal wiring layer is made of a softer material than that of the first interlayer insulating layer. The metal wiring layer at least partially overlaps with the interconnection region in the stacked direction of the layers, and the area of metal wiring layer overlapping with the interconnection region includes notches that extend through the metal wiring layer in the stacked direction and separate the metal wiring layer in the layer direction. Portions of the first interlayer insulating layer are embedded in the notches. This enables the size of the semiconductor device to be reduced by efficiently utilizing the underlying layers of the bonding pad while preventing cracking in these layers.

Semiconductor device and fabrication method thereof

A selected memory cell is correctly read even when a threshold value of a non-selected memory cell that shares a word line is low. When reading a memory cell MC , a discharge transistor select circuit selectively discharges a bit line BL connected to the memory cell MC and two bit lines BL and BL that are adjacent to the bit line BL . A precharge control circuit fixes to a precharge voltage a center bit line among five bit lines that include a bit line BL connected to the memory cell MC and four bit lines that are adjacent to the bit line BL and brings the remaining bit lines into a floating state with the precharge voltage. Thus, the potential of the bit line BL is prevented from being lowered as a consequence of a leak current occurring via the non-selected memory cell MC when the threshold value of the selected memory cell MC is high, by which the erroneous determination that the ON-state is provided is prevented from being made.

Nonvolatile semiconductor storage device capable of correctly reading selected memory cell and read method

According to the present invention, a bitline precharge circuit for a semiconductor memory device is provided. The semiconductor memory device includes: a plurality of word lines arranged in a row direction; a plurality of bitlines forming a plurality of bitline pairs arranged in a column direction; and a plurality of memory cells connected between each of the plurality of bitline pairs via a plurality of switching elements, the switching elements being controlled by respectively different ones of the word lines. The bitline precharge circuit charges a potential on all of the bitlines to a precharge level which is approximately intermediate between a power supply voltage and a ground voltage before a write operation or a read operation is performed and is characterized by including a write precharge circuit for further varying the potential on the bitlines, which has been charged to the precharge level, by a predetermined level before the write operation is performed.

Bitline precharge circuit for semiconductor memory device

A buffer circuit according to the present invention includes an input terminal for inputting an input signal, an inverter circuit for inverting the input signal and outputting the inverted input signal to an output terminal, wherein the inverter circuit has a plurality of PMOS transistors and a plurality of NMOS transistors; each of the plurality of PMOS transistors has a source connected to a power source, a drain connected to the output terminal, and a gate connected to the input terminal; each of the plurality of NMOS transistors has a source connected to a ground, a drain connected to the output terminal, and a gate connected to the input terminal; and the gate of at least one of the plurality of PMOS transistors and NMOS transistors is connected to the input terminal via a fuse element which can be selectively disconnected.

Buffer circuits with changeable drive characteristic

A static memory cell is connected to a first bit line and a second bit line, and includes the following: a first inverter section having a first input and a first output; a second inverter section having a second input connected to a first output through a first node, and a second output connected to the first input through a second node; a first switching section for allowing or not allowing conduction between the first bit line and the first node; a first capacitor arranged between the second bit line and the first node; a second switching section for allowing or not allowing conduction between the second bit line and the second node; and a second capacitor arranged between the first bit line and the second node.

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Matsubara, Japan

Atsushi Semi