Texas Instruments Corporation

Atsushi Satoh

Hiroyuki Yoshida

Toshiyuki Nagata

Masayuki Moroi

Shuzoh Shiosaki

In a DRAM array using a capacitor-under-bitline (CUB) layout, the plate layer of the capacitor is significantly reduced in area to reduce misalignments in connections between the bitline and the underlying transistors.

Reduced size plate layer improves misalignments for CUB DRAM

A memory cell array ( ) is disclosed having variable pitch word lines and bit lines. The word lines include central word lines ( ) having a first pitch, and peripheral word lines ( ), situated proximate to the edge of the array ( ), having a second pitch that is greater than the first pitch. In a similar fashion, the bit lines include central bit lines ( ) having a third pitch, and peripheral bit lines ( ), situated proximate to the edge of the array ( ), having a fourth pitch that is greater than the third pitch. The increase in word line and bit line pitch can reduce the adverse results of proximity effects caused by the junction of the dense array features with the relatively open features of the adjacent periphery circuits.

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Atsushi Satoh