Fujitsu Corporation

Fujitsu Microelectronics Limited

Incs, Inc.

Atsushi Sakurai

Nobukazu Koizumi

Yoshinobu Yamamoto

Seiki Sato

Shinjiro Yamada

Katsuji Iwasaki

Shosuke Mori

Nobuhide Takaba

Satoshi Aoki

Tatsuya Suzuki

Atsuo Suzuki

Takao Ikeda

Daichi Ninagawa

Kazuhiro Kuwahara

Junya Uramoto

Atsushi Miyadera

For the purpose of providing a simulation model allowing gate simulation but is capable of keeping the circuit information on the functional block (IP) secret, a method of generating a simulation model provided herein by the present invention comprises a step of generating a net list containing circuit information of an electronic circuit using a functional block; and a step of deleting the circuit information based on the net list, and generating a gate simulation model carrying out a timing simulation, including logic information and delay information between input/output of the functional block.

Method of generating simulation model while circuit information is omitted

A processing apparatus includes a memory capable of storing data, a butterfly arithmetic unit for performing butterfly computation processes, and a bit-reversed order shuffle processing unit for writing results obtained by butterfly computation processes performed by the butterfly arithmetic unit at addresses in the memory after bit-reversed order shuffle instead of writing the results at addresses in the memory in processing order. The data written by the bit-reversed order shuffle processing unit are discrete fast Fourier transform results.

Processing apparatus

The present invention provides a die design support method and system capable of reducing the time-period required for a die design, allowing an unskilled die engineer to perform a die design without difficulties, and coping with a product design change in a short time-period. A standard die design procedure is stored as 'master die data' in advance using a function of a CAD system or the like. When a product design data is entered, the design procedure is automatically executed to the design data in accordance with the stored master die data. Preferably, the entire master die data is divided into a plurality of processes, such as a process of creating a scaling model, and a process of creating a parting model.

Die design support method and die design support system

The present invention resolves the problems of conventional top down hierarchical layout design methods by including the following in a top down hierarchical layout design method using soft block, in addition to determining the arrangement of block pin (called &ldquo;soft pin&rdquo;) in soft block, generating second block pin having the same potential as existing block pin; and moving block pin position to position opposite the block pin to be connected. The layout tool program of the present invention is therefore provided the functions of moving and generating soft pin, whereby the top level signal wiring in the region among the blocks is optimized, delay time is minimized, and the use of wasteful wiring channel is avoided for any combination of blocks.

LSI manufacturing method and recording medium for storing layout software

A multiprocessor system used, for example, in a personal computer, wherein different types of microprocessors are used independently of the architecture of each microprocessor. The system includes a control register, a control circuit, and a common peripheral circuit mounted, for example, on a main board, and a plurality of kinds of microprocessors each mounted, for example, on a sub-board connected to the main board. The control circuit transmits a halt request signal to a first microprocessor which is currently operating, in response to coincidence between an output signal of the control register and the status signal indicating that a second microprocessor is in a halt condition, when the output signal of the control register is changed by the first microprocessor. Then, the control circuit releases a halt request signal applied to the second microprocessor in response to coincidence between a status signal indicating that the first microprocessor has entered into a halt condition and the output signal of the control register.

Multiprocessor system

Growing community of inventors

Kawasaki, Japan

Atsushi Sakurai