Hitachi, Ltd.

Other

Elpida Memory, Inc.

Hitachi Ulsi Systems Co., Ltd.

Atsushi Ogishima

Masayuki Kojima

Hiroyuki Uchiyama

Kozo Watanabe

Norio Suzuki

Kiyonori Ohyu

Shoji Shukuri

Kenichi Kuroda

Masahiro Moniwa

Syunichi Hashimoto

Nozomu Matsuda

Shuji Ikeda

Yutaka Kobayashi

Toshiaki Yamanaka

Natsuki Yokoyama

Shinichiro Kimura

Akio Nishida

Yoshitaka Tadaki

Osamu Tsuchiya

Hisashi Nakamura

Norio Ishitsuka

Yasuko Yoshida

Kazuo Nojiri

Toshihiro Sekiguchi

Atsuyoshi Koike

Jun Murata

Hiromichi Enami

Osamu Kasahara

Hiroyuki Miyazawa

Kikuo Kusukawa

Akira Takamatsu

Keiji Okamoto

Hiroko Kaneko

Shinichi Horibe

Michimasa Funabashi

Toshio Maeda

Masaki Nagao

Hiroyuki Ichizoe

Maki Shimoda

Yasuo Kiguchi

Kazuya Kadota

Tadashi Chikahara

Masato Sadaoka

Takashi Aoyagi

Yuji Hara

Hirotaka Kobayashi

A semiconductor integrated circuit device is provided which includes an active region, a shallow groove isolation adjacent to the active region, and a semiconductor element formed in the active region and having a gate. The sum of a width of the active region and a width of the shallow groove isolation constitutes a minimum pitch in the direction of a gate width of the gate, and the width of the active region is set larger than one-half of the minimum pitch.

Semiconductor integrated circuit device and a method of manufacturing the same

A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodesare formed via a gate insulating filmon the main surface of a semiconductor substrate, and on side surfaces of each of the gate electrodes there is formed a first side wall spacercomposed of silicon nitride and a second side wall spacercomposed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holesandin a self-matching manner with respect to the first side wall spacersand connecting portion is formed connecting a conductorto a bit line BL. In addition, in the N channel MISFETs Qnand Qn, and in the P channel MISFET Qpin areas other than the DRAM memory cell area, high density N-type semiconductor areasandare formed, as well as a high density P-type semiconductor areais formed in a self-matching manner with respect to the second side wall spacers

Semiconductor integrated circuitry and method for manufacturing the circuitry

A memory cell of a DRAM is reduced in size by making the width of a bit line finer than the minimum size determined by the limit of resolution of a photolithography. The bit line is made fine by forming a silicon oxide film on the inside wall of a wiring trench formed in a silicon oxide film and by forming the bit line inside the silicon oxide film. The silicon oxide film formed in the trench is deposited so that the silicon oxide film has a thickness thinner than half the width of the wiring trench and in the fine gap inside the silicon oxide film is buried a metal film to be the material of the bit line.

Semiconductor integrated circuit device and the process of manufacturing the same having poly-silicon plug, wiring trenches and bit lines formed in the wiring trenches having a width finer than a predetermined size

Semiconductor integrated circuit device and the process of manufacturing the same for reducing the size of a memory cell by making the width of a bit line than a predetermined minimum size

A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes are formed via a gate insulating film on the main surface of a semiconductor substrate , and on side surfaces of each of the gate electrodes there is formed a first side wall spacer composed of silicon nitride and a second side wall spacer composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes and in a self-matching manner with respect to the first side wall spacers and connecting portion is formed connecting a conductor to a bit line BL. In addition, in the N channel MISFETs Qn and Qn , and in the P channel MISFET Qp in areas other than the DRAM memory cell area, high density N-type semiconductor areas and are formed, as well as a high density P-type semiconductor area is formed in a self-matching manner with respect to the second side wall spacers

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND THE PROCESS OF MANUFACTURING THE SAME HAVING POLY-SILICON PLUG, WIRING TRENCHES AND BIT LINES FORMED IN THE WIRING TRENCHES HAVING A WIDTH FINER THAN A PREDETERMINED SIZE

In a semiconductor integrated circuit device having a memory cell which includes a MIS.FET and a capacitance element, the conductivity type of a low-resistance polysilicon film which constitutes the gate electrode ( ) of the memory cell selecting MIS.FET (Q) of n-channel type constituting the memory cell is set at p -type in order to enhance the refresh characteristics of the memory cell.

Semiconductor integrated circuit device and the method of producing the same

Grooves are defined in a substrate having device isolation regions by dry etching using silicon nitride films and side wall spacers as masks. Thereafter, the side wall spacers lying on side walls of the silicon nitride films are removed and the substrate is subjected to thermal oxidation, whereby the surface of the substrate at a peripheral portion of each active region is subjected to so-called round processing so as to have a sectional shape having a convex rounded shape.

Semiconductor integrated circuit device and method of manufacturing involving the scale-down width of shallow groove isolation using round processing

A semiconductor integrated circuit device including a plurality of holes in an interlayer insulating film beneath a bonding pad wherein a plug is buried in the respective holes and is made of the same conductive film (W/TiN/Ti) as a plug in a through-hole. Any wire as a second layer is not formed in a lower region of the bonding pad. The plug buried in the holes is connected only to the upper boding pad and is not connected to a lower wire.

Process for multilayer wiring connections and bonding pad adhesion to dielectric in a semiconductor integrated circuit device

It is an object of the present invention to provide a technology of a semiconductor integrated circuitry that allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operated faster. In a method for manufacturing such a semiconductor integrated circuitry of the present invention, at first, gate electrodes are formed via a gate insulating film on the main surface of a semiconductor substrate , and on side surfaces of each of the gate electrodes is formed the first side wall spacer composed of silicon nitride and the second side wall spacer composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area are opened connecting holes and in a self-matching manner with respect to the first side wall spacers and are formed connecting portion connecting a conductor to a bit line BL. In addition, in the N channel MISFETs Qn and Qn , and in the P channel MISFET Qp in areas other than the DRAM memory cell area are formed high density N-type semiconductor areas and , as well as a high density P-type semiconductor area in a self-matching manner with respect to the second side wall spacers

Semiconductor integrated circuit device and method for manufacturing the same

In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, then insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved. At the same time, upon chemical mechanical polishing, a silicon substrate can be prevented from being exposed at the central portion of the memory mat portion and the insulating film can be prevented from being left on the silicon nitride film near the outer periphery, thereby making it possible to form elements having uniform electrical characteristics on all active regions of the memory mat portion.

Method of manufacturing semiconductor devices

Method of forming a MISFET device with a bit line completely surrounded by dielectric

Growing community of inventors

Tachikawa, Japan

Atsushi Ogishima