Globalfoundries Inc.

International Business Machines Corporation

Globalfoundries U.S. Inc.

Atsushi Ogino

Brian Joseph Greene

Jim Shih-Chun Liang

Vikrant Kumar Chauhan

Jim S Liang

Dureseti Chidambarrao

Erdem Kaltalioglu

Roger Allan Quon

Edward P Maciejewski

Vara Govindeswara Reddy Vakada

Mankyu Yang

Motoi Ichihashi

Justin C Long

Prianka Sengupta

Stephen E Greco

Rajiv V Joshi

Baozhen Li

Michael Patrick Chudzik

Hsueh-Chung Chen

Andrew Herbert Simon

Terry Allen Spooner

Naftali Eliahu Lustig

David S Wolpert

Steven Paul Ostrander

Louis DeWolf Lanzerotti

Ravi Prakash Srivastava

Michael S Gray

Shafaat Ahmed

Tuhin Sinha

Noam Jungmann

Joyeeta Nag

Craig Child

Elazar Kachir

Matthew Thomas Guzowski

Keith Donegan

Martin O'Toole

Ahmed Hassan

Brendan O'Brien

Nan Jing

Lin Hu

Kong Boon Yeap

Sean Reidy

Domingo A Ferrer Luppi

Bishan He

Klimentiy Shimanovich

Sadanand Vinayak Despande

An integrated circuit includes a semiconductor substrate and integrated circuitry on the semiconductor substrate. The integrated circuitry includes a static random access memory (SRAM) array including a conductive line and an assist circuit having a boost capacitor coupled to boost a voltage on the conductive line. The boost capacitor includes first and second plates. The integrated circuit further includes a sense circuit having an input coupled to one of the first and second plates of the boost capacitor and an output and a sample circuit coupled to the output of the sense circuit. The sample circuit is configured to detect a short circuit in the boost capacitor based on a state change at the output of the sense circuit.

Short circuit detection in a read/write assist capacitor of a memory

A metal insulator metal capacitor and method for fabricating a metal insulator metal capacitor (MIMcap) are disclosed. A first level metal pattern is embedded in a first dielectric layer over a substrate. The first level metal pattern has a top surface co-planar with a top surface of the first dielectric layer. In a selected etch step, either one of the first metal pattern or the first dielectric is etched to form a stepped top surface. A conformal insulating layer on the stepped top surface. The MIMcap is formed on the conformal insulating layer in a conformal manner.

High performance metal insulator metal capacitor

Methods of self-aligned multiple patterning. A hardmask is deposited over an interlayer dielectric layer. A mandrel is formed over the hardmask. A block mask is formed that covers a first lengthwise section of the mandrel and that exposes second and third lengthwise sections of the mandrel. After forming the block mask, the second and third lengthwise sections of the mandrel are removed to define a pattern including respective first and second mandrel lines that are separated from each other by the first lengthwise section of the mandrel. The first mandrel line and the second mandrel line expose respective portions of the hardmask, and the first lengthwise section of the mandrel line covers another portion of the hardmask. The pattern is transferred to the hardmask with an etching process, and subsequently transferred to the interlayer dielectric layer with another etching process.

Multiple patterning with mandrel cuts defined by block masks

A structure including a plurality of dielectric regions is described. The structure can include a rivet cell. The rivet cell can include a set of stacked vias. The rivet cell can extend through a stress hotspot of the structure. A length of the rivet cell can thread through at least one dielectric region among the plurality of dielectric regions. The rivet cell can be among a number of rivet cells inserted in the stress hotspot. The stress hotspot can be among a plurality of stress hotspots across the structure. A length of the rivet cell can be based on a model of a relationship between the length of the rivet cell and an energy release rate of the structure. The rivet cell can thread through an interface between a first dielectric region and a second dielectric region having different dielectric constants.

Stacked via rivets in chip hotspots

The present disclosure relates to semiconductor structures and, more particularly, to a dual airgap structure and methods of manufacture. The structure includes: a lower metal line; a plurality of upper metal lines; and a first airgap between the lower metal line and at least one upper metal line of the plurality of upper metal lines.

Dual airgap structure

Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a device-under-testing that has one or more source/drain regions and a first metallization level arranged over the device-under-testing. The first metallization level includes one or more first interconnect lines. The structure further includes a contact level having one or more first contacts arranged between the first metallization level and the device-under-testing. The one or more first contacts directly connect the one or more first interconnect lines with the one or more source/drain regions. The structure further includes a second metallization level arranged over the first metallization level. The second metallization level has a first test pad and one or more second interconnect lines connecting the one or more first interconnect lines with the first test pad.

Test structures connected with the lowest metallization levels in an interconnect structure

Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a test pad, a device-under-testing having one or more source/drain regions, and a metallization level arranged over the device-under-testing. The metallization level includes one or more interconnect lines that are connected with the test pad. One or more contacts, which are arranged between the metallization level and the device-under-testing, directly connect the one or more interconnect lines with the one or more source/drain regions.

Test structure leveraging the lowest metallization level of an interconnect structure

Device structures and fabrication methods for an on-chip resistor. A resistor body is formed on an interlayer dielectric layer of a contact level. A contact is formed that extends vertically through the interlayer dielectric layer. One or more dielectric layers are formed over the contact level, and a metal feature is formed in the one or more dielectric layers. The metal feature is at least in part in direct contact with a portion of the resistor body.

On-chip resistors with direct wiring connections

Disclosed herein is an integrated circuit (IC) including a first metal layer running in a first direction, a second metal layer running in a second direction perpendicular to the first direction, the second metal layer above the first metal layer and a third metal layer running in the first direction above the second metal layer. A viabar electrically connects the first metal layer to the third metal layer, the viabar running in the first direction wherein the viabar vertically extends from the first metal layer to the third metal layer. A method of manufacturing the IC is provided.

Interconnect structure having power rail structure and related method

A method of forming a semiconductor structure includes forming a first insulating layer containing a first metal layer embedded therein and on a surface of a semiconductor substrate. The method further includes forming an inter-layer dielectric (ILD) layer on the first insulating layer, and forming at least one via trench structure including a first metallization trench and a via in the ILD layer. In addition, the method also includes depositing a metal material to form a first metallization layer in the first metallization trench, a via contact in the via, and a second metal layer on top of at least a portion of the first metal layer in the opening of the first insulating layer. The first metal layer and the second metal layer constitute a multilayer metal contact located in the opening of the first insulating layer.

Method to reduce resistance for a copper (Cu) interconnect landing on multilayered metal contacts, and semiconductor structures formed therefrom

Devices and methods of fabricating integrated circuit devices using semi-bidirectional patterning are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a dielectric layer, a first, a second, and a third hardmask layer, and a lithography stack; patterning a first set of lines; patterning a second set of lines between the first set of lines; etching to define a combination of the first and second set of lines; depositing a second lithography stack; patterning a third set of lines in a direction perpendicular to the first and second set of lines; etching to define the third set of lines, leaving an OPL; depositing a spacer over the OPL; etching the spacer, leaving a vertical set of spacers; and etching the second hardmask layer using the third hardmask layer and the set of vertical spacers as masks.

Methods of forming semiconductor devices using semi-bidirectional patterning

Structures for an on-chip capacitor and methods of forming an on-chip capacitor. A metal terminal is formed that has a side edge. Metal fingers are formed that have a parallel arrangement. Floating islands comprised of a metal are formed and are electrically isolated from the metal fingers. Each of the metal fingers has an end and extends from the side edge of the metal terminal toward the end. Each of the floating islands is arranged in a spaced relationship with the end of a respective one of the metal fingers.

On-chip capacitors with floating islands

Method to reduce resistance for a copper (CU) interconnect landing on multilayered metal contacts, and semiconductor structures formed therefrom

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Fishkill, NY, United States of America

Atsushi Ogino