Seiko Epson Corporation

Atsushi Obinata

Tomokazu Yamada

Kazuhito Fujisawa

Chisato Higuchi

Katsumi Okina

A liquid ejecting apparatus includes a differential signal output circuit that outputs a pair of differential signals based on an original control signal, a pair of first signal wirings that are electrically coupled to the differential signal output circuit and propagate the differential signals, a first receiving circuit that is electrically coupled to the first signal wirings, a second receiving circuit that is electrically coupled to the first signal wirings, and an ejector that includes a drive element and that ejects a liquid from a nozzle by driving the drive element, in which the first receiving circuit outputs a control signal for controlling driving of the drive element based on the differential signals, power consumption of the first receiving circuit is larger than power consumption of the second receiving circuit, and the first receiving circuit and the second receiving circuit are electrically coupled by a second signal wiring.

Liquid ejecting apparatus, drive circuit, and integrated circuit

A liquid ejecting apparatus includes a drive signal output circuit, a control signal output circuit, a differential signal output circuit, and a head unit, in which the head unit includes an integrated circuit that receives a first drive signal and outputs a second drive signal, and an ejector that ejects liquid from nozzle, and the integrated circuit includes a drive signal input terminal that inputs a first drive signal, a first signal input terminal that inputs a first signal, a second signal input terminal that inputs a second signal, a differential signal receiving circuit that receives the first signal and the second signal, and outputs the control signal, a drive signal selection circuit that outputs the second drive signal based on the control signal and the first drive signal, and a drive signal output terminal that outputs the second drive signal to the ejector.

A display control device includes a first interface unit that receives display information of a first display method that includes image data and a control information setting unit that sets control information used for controlling display of an image in the display unit in accordance with setting information that specifies a display method. The display control device further includes an image data conversion unit that converts, if a second display method is specified by the setting information, the image data of the first display method type to image data of the second display method type in accordance with the control information. The display control device also includes a second interface unit that outputs the image data of the first or the second display method type in accordance with the setting information, and outputs signals for controlling the display unit in accordance with the control information.

Display control device and method, semiconductor integrated circuit device, and display device

An image processing device that supplies image data to a driver section of a display panel includes an encoding section that encodes image data on a block-by-block basis to generate encoded data, the image data corresponding to one scan line of an input image, the image data being divided into a plurality of blocks, a memory that stores the encoded data from the encoding section, and a decoding section that decodes the encoded data from the memory on a block-by-block basis to generate decoded data, the decoded data from the decoding section being supplied to the driver section.

Image processing device, image processing method, and electronic instrument

A display controller comprising: an image data input interface; a first image processing section for a first processing operation including at least a turning operation to turn an orientation of an image of the image data with a first turning angle or a mirror image reversing operation; a second image processing section for a second processing operation including at least a turning operation to turn an orientation of an image of the image data with a second turning angle or a mirror image reversing operation; an image data compressing section compressing the image data after the first processing operation; a memory for the compressed data where the image data, after the compressing operation, are stored; a host interface to/from which the imaged data stored in the memory are input and output; and a display driver interface outputting the image data, after the second processing operation, to the display driver.

Display controller, electronic device, and method of supplying image data

The display controller includes a first memory storing image data and being accessed with a sequential access operation having a shorter access time than that of a random access operation, a second memory storing image data and consuming a less power than the first memory does at the time of the access operation and a data transfer control part performing an image data transfer control between the first memory and the second memory. The data transfer control part performs a transfer control to transfer the image data from the first memory to the second memory and transfer the image data written in the second memory after the image processing from the second memory to the first memory. The display controller supplies the image data in the first memory to a display driver.

Display controller, electronic equipment and method for supplying image data

A semiconductor device including: a DRAM which is a volatile memory; a PLL circuit which outputs an operation clock signal generated by multiplying an input clock signal; a circuit block which operates in synchronization with the operation clock signal; first and second refresh controllers for requesting a refresh operation of the DRAM; and a memory controller which arbitrates between an access request for the DRAM from the circuit block and a refresh request from the first refresh controller. In a first mode in which the PLL circuit operates, the first refresh controller issues the refresh request to the DRAM controller. In a second mode in which the operation of the PLL circuit stops, the second refresh controller issues the refresh request, the refresh request bypassing the DRAM controller.

Semiconductor device and electronic instrument

A semiconductor integrated circuit is provided in which power consumption of each functional block can be determined. The semiconductor integrated circuit comprises: first through third signal processing circuits each operating in synchronization with first through third externally supplied clock signals; first through third counters each counting first through third clock signals; a bus interface circuit outputting a plurality of count values that the first through third counters counted; a clock enable signal generating circuit to generate first through third clock enable signals each controlling the supply of the first through third clock signals to the first through third signal processing circuits; and a counter control circuit supplying a plurality of counter reset signals and a plurality of counter enable signals for resetting and operating the first through third counters, respectively.

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Hachioji, Japan

Atsushi Obinata