Hitachi, Ltd.

Renesas Technology Corp.

Other

Hitachi Ulsi Systems Co., Ltd.

Hitachi Ulsi Engineering Corp.

Hitachi Vlsi Engineering Corp.

Hitachi Device Engineering Co., Ltd.

Vlsi Engineering Corporation

Atsushi Nozoe

Shoji Kubono

Michitaro Kanamitsu

Keiichi Yoshida

Tetsuya Tsujikawa

Ken Matsubara

Hiroaki Kotani

Eiji Yamamoto

Takayuki Kawahara

Yoshinori Takase

Katsutaka Kimura

Hiroshi Sato

Satoshi Noda

Hitoshi Miwa

Hideaki Kurata

Toshinori Harada

Takayuki Yoshitake

Yutaka Kobayashi

Kunihiro Katayama

Kazumasa Yanagisawa

Goro Kitsukawa

Kazuo Nakamura

Masayuki Nakamura

Tetsurou Matsumoto

Shoji Wada

Tetsu Udagawa

Yoshitaka Kinoshita

Kyoko Ishii

Tatsuyuki Ohta

Takashi Horii

Hiromi Tsukada

Yoshiaki Ouchi

Kazuo Mihashi

Naoki Kobayashi

Takashi Kobayashi

Tatsuya Ishii

Takayuki Tamura

Kazuyoshi Oshima

Shunichi Saeki

Tomoyuki Fujisawa

Yoshinori Sakamoto

Toshihiro Tanaka

Hitoshi Kume

Toshio Sasaki

A non-volatile storage device () has non-volatile memory units (FARYto FARY), buffer units (BMRYto BMRY) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside. Consequently, it is possible to reduce the overhead of a data transfer for reading/writing data from/to the non-volatile storage device.

Non-volatile memory having multiple erase operations

A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.

Nonvolatile semiconductor storage device

Nonvolatile memory with independent access capability to associated buffer

A memory system includes a plurality of nonvolatile memory chips (CHPand CHP) each having a plurality of memory banks (BNKand BNK) which can perform a memory operation independent of each other and a memory controller () which can control to access each of said nonvolatile memory chips. The memory controller can selectively instruct either a simultaneous writing operation or an interleave writing operation on a plurality of memory banks of the nonvolatile memory chips. Therefore, in the simultaneous writing operation, the writing operation which is much longer than the write setup time can be performed perfectly in parallel. In the interleave writing operation, the writing operation following the write setup can be performed so as to partially overlap the writing operation on another memory bank. As a result, the number of nonvolatile memory chips constructing the memory system of the high-speed writing operation can be made relatively small.

Memory system and memory card

There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases. In the non-volatile memory of the invention comprising the AND type memory array in which a plurality of memory cells are connected in parallel between the local bit lines and local drain lines, the local drain lines are precharged by supplying thereto a comparatively higher voltage from the common drain line side (opposite side of the main bit lines), the main bit lines are selectively precharged by applying thereto the voltage of 0V or a comparatively small voltage depending on the write data and thereafter a drain current is applied only to the selected memory cells to which data is written by applying the write voltage to the word lines in order to implant the hot electrons to the floating gate.

Nonvolatile memory and method of programming the same memory

Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the overprograming condition, the program data is no longer required to be again received from the external device.

Semiconductor, memory card, and data processing system

A non-volatile memory system is provided with a control device and non-volatile memory devices, each including memory cells and data latches. The control device supplies commands to the non-volatile memory devices, including a write command, and first and second read commands. When the control device supplies the write command with write address information and data for storing in the non-volatile memory device, it stores the data to the data latches and then to the memory cells, and then verifies storage. When the control device supplies the first read command with read address information, the nonvolatile memory device reads data stored in the memory cells to the data latches and then outputs the data in the data latches to the control device. When the control device supplies the second read command, the non-volatile memory device outputs data in the data latches to the control device.

Non-volatile memory system including a control device to control writing, reading and storage and output operations of non-volatile devices including memory cells and data latches

Data are generated based on additional write data input to data latch circuits (DLR and DLL) and data read from memory cells (MC) to program non-volatile memory cells in a write state into the same write state and to program non-volatile memory cells in an erase state into a write state indicated by the additional write data. The generated data are latched in the data latch circuits to perform a logical synthesis process for additional writing. Even after the additional write operation, the logically synthesized data remain in the data latch circuits, and the latched data can be reused against abnormality in writing. This eliminates the need for receiving write data again from the outside when the additional write operation is to be retried.

Semiconductor device, data processing system and a method for changing threshold of a non-volatile memory cell

A nonvolatile memory device having an error correcting function, capable of outputting read-out data (uncorrected) while simultaneously generating syndromes. After the syndrome formation, the memory device outputs an error status signal (ERR) and, depending on the presence or absence of an externally supplied request (SC), again outputs read-out data (this time corrected).

Memory device and memory card

Nonvolatile memory system

A non-volatile memory device having a plurality of memory cells and a control circuit. The control circuit receives operation commands from outside the device and controls the operation of the device according to the commands. The commands include read commands and write commands. In a read command, the control circuit reads data in the memory cells and outputs it. In a write command, the control circuit controls the inputting of data to data latch circuits and then to memory cells. The control circuit provides status information indicating whether the writing of data is a success or a failure.

Non-volatile memory device

A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.

Semiconductor integrated circuit and data processing system

Growing community of inventors

Hino, Japan

Atsushi Nozoe