Sony Corporation

Atsushi Narita

Etsuro Yamauchi

Yasuhide Mogi

Tatsuya Narahara

Keiichi Yoshioka

Norihiro Nagai

Ippei Tambata

Ryo Takaoka

Naoyuki Miyada

Kuriko Takeshima

An information processing device for providing a program selected on the basis of a predetermined theme among recorded programs and programs to be received to a user. A special program is generated by selecting a predetermined program on the basis of a predetermined theme such as 'person of the today', 'hot drama', among recorded programs and programs to be received to a user and the contents of the selected program is displayed on a screen as information of a recommendation program. The contents of the special program are changed according to preference of the user, a displaying time of the screen, and setting by the user.

Information processing device, method of processing information, and program

An image processing apparatus enabling alpha blending or other image processing during bit block transfer (bitblt), wherein the selectorselects one of the primitive data S, the image data Sand the image data Sthat are used for the host-local transfer, and outputs the data to the alpha blend circuit. According to the control signal S, the alpha blend circuitturns on or turns off alpha blending. The selectorselects either the image data Sor the image data Sand writes the data to the DRAM

Image processing apparatus

An image processing apparatus capable of performing a refresh operation without causing a drop in performance, an increase in cost, or damage to the apparatus. The apparatus further being capable of achieving a reduction in power consumption, and being provided with a memory I/F circuit able to not only refresh, for example, four DRAM modules simultaneously, but also capable of refreshing two DRAM modules at a same timing, then refreshing the remaining two DRAM modules simultaneously at a next timing, or refreshing the four DRAM modules one by one in order based on given refresh control data, and controlling the timing of the refresh operation for each divided DRAM module.

An image data processing apparatus capable of performing processing at a high speed comprising a DRAM for storing display data including a plurality of first pixel data respectively indicating colors of a plurality of pixels arranged in a matrix and able to be simultaneously written with a plurality of first pixel data. Memory controllers are provided with a plurality of pixel data generation circuits provided corresponding to the plurality of first pixel data to be simultaneously written for performing color blending using the second pixel data and the third pixel data for blending a color indicated by corresponding second pixel data and a color indicated by third pixel data stored in the write address by a predetermined blending ratio to generate a new color so as to generate the first pixel data indicating the new color.

Image data processing apparatus

A video signal format converting circuit is disclosed, comprising a signal converting matrix circuit and a filter circuit that is constructed of a time delaying device for a video signal corresponding to a standard television format. When a digital video signal corresponding to a first video signal format is converted into a second video signal format that is different from the first video signal format and then output, the time delaying device of the filter circuit is used as a delaying circuit. The output signal of the delaying circuit or the video signal corresponding to the standard television signal format is selectively output. While or after the video signal corresponding to the first video signal format is converted into the video signal corresponding to the second signal format, the video signal is modified so as to protect it from being copied.

Growing community of inventors

Tokyo, Japan

Atsushi Narita