Nec Electronics Corporation

Kabushiki Kaisha Toshiba

Nec Corporation

Sony Corporation

Casio Computer Co., Ltd.

Renesas Electronics Corporation

Mitsubishi Heavy Industries Limited

Atsushi Nakagawa

Satoshi Yamamoto

Hiroyuki Takahashi

Hideo Inaba

Takuya Hirota

Takao Suzuki

Yoshiyuki Kato

Masahiro Yoshida

Masatoshi Sonoda

Noriaki Komatsu

Tetsuro Narikawa

Susumu Takano

Kiyotaka Tsuji

Muneyuki Suzuki

Eiji Konishi

Kozo Matsushita

Hidetaka Yoshikawa

Toru Takahama

Yasunari Kawaguchi

Yoshiyuki Katou

Yutaka Seki

Masaki Miyata

Kouichi Gotou

Kosuke Yanagi

Yuuji Torige

Takuya Kera

A turbine includes: a rotor having a rotor body, and a plurality of rotor blades; a casing covering the rotor; and a plurality of stator blades, wherein the stator blades each include a stator blade body having formed on the surface thereof a suction part that extends in the radial direction and can suction at least a portion of working fluid, a nozzle inner peripheral member provided inward of the stator blade body in the radial direction, and a plurality of seal fins protruding inward in the radial direction from the inner peripheral surface of the nozzle inner peripheral member, and an ejection port for ejecting the working fluid guided from the suction part is formed in the nozzle inner peripheral member and in a portion of seal fins more on the other side than the seal fin most on one side in the axial line direction.

Turbine

A projector apparatus includes a projection unit that projects an image, a projection direction variable unit configured to mechanically change a direction of the image to be projected by the projection unit, an acquiring unit that acquires the image projected by the projection unit onto a target of projection, and a control unit that determines a direction of projection to be changed by the projection direction variable unit, based on information on a plurality of projection images acquired by the acquiring unit.

Projector apparatus, projection method, and storage medium

A projection control device includes a hardware processor. The hardware processor acquires a feature of a projection surface. The hardware processor determines a first area in which a first projection image corrected based on the acquired feature of the projection surface is projected and a second area that is other than the first area and in which a second projection image corrected based on the feature of the projection surface is projected, within a projection area projectable, by a projection device, on the projection surface. Then, the hardware processor controls the projection device to project the first projection image in the first area and project the second projection image in the second area.

Projection control device, projection control method, and non-transitory storage medium

A gas circuit breaker includes a hermetically-sealed container filled with an arc extinguishing gas, a fixed contact arranged within the container, a movable contact arranged to face the fixed contact and configured to move in an axial direction of the container, the movable contact capable of contacting or separating from the fixed contact, an insulating operation rod having one end connected to an end of the movable contact opposite to the fixed contact through a link at an angle of about 90 degrees with respect to the movable contact, and an actuator arranged in a substantially coaxial relationship with the insulating operation rod, the actuator including an output shaft transferring a driving force for the operation of the movable contact to the other end of the insulating operation rod.

Gas circuit breaker

A wireless communication device according to embodiments includes a position detection unit configured to detect the position of the wireless communication medium in a moving path, and a control unit configured to control communication based on the detection signal from the position detection unit.

Wireless communication device and medium processing apparatus

In one embodiment, a semiconductor memory device includes a plurality of pairs of bit lines, each of said pairs including a first bit line, a second bit line, a memory cell coupled to said first bit line, a sense amplifier determining the logical value stored in the memory cell according to a potential difference between the first and the second bit line, a reference voltage generation circuit, and a reference voltage supply switch coupling an output of the reference voltage generation circuit to the second bit line.

Dynamic random access memory device suppressing need for voltage-boosting current consumption

A semiconductor storage device according to one aspect of the present invention includes a DRAM cell including one transistor and one capacitor, in which one of a first voltage and a second voltage is applied to a gate of the transistor, the first voltage being a selected voltage, and the second voltage being a non-selected voltage, a voltage difference between the first voltage and the second voltage is larger than a voltage difference between a power supply voltage and a ground voltage, and one of the ground voltage and the power supply voltage which is closer to the non-selected voltage is applied to a back gate of the transistor irrespective of selection or non-selection.

Semiconductor storage device

A radio communication apparatus includes a carriage path through which a radio communication medium is carried, a communication antenna provided in the carriage path, and a detector provided on an upstream side of the antenna in a carrying direction of the moving radio communication medium. The detector detects the passing radio communication medium. A radio main unit detects the radio communication medium by using the detector, and transmits a polling command to the radio communication medium at a proper timing on the basis of a detection signal from the detector. Thereby, it is possible to transmit a polling command from the radio main unit to the radio communication medium at a proper timing when the radio communication medium comes to a communication area of the antenna.

Radio communication apparatus and radio communication method

A semiconductor device includes a first memory; and a voltage adjusting portion configured to receive a first voltage, a second voltage higher than the first voltage, and a third voltage higher than the second voltage. The first memory includes: a memory cell configured to be connected to a word line and a bit line, a word-line driving circuit configured to drive the word line, and a sense amplifier configured to sense information stored in the memory cell. The voltage adjusting portion includes: a voltage modifying circuit configured to step down or boost up the third voltage at a predetermined mode to generate a fourth voltage higher than the second voltage, and supply the fourth voltage to the sense amplifier or the word-line driving circuit.

Semiconductor device that uses a plurality of source voltages

A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.

Semiconductor memory with a delay circuit

Disclosed is a semiconductor memory device having memory cells that are in need of refresh for data retention, includes control circuits for necessarily generating the refresh immediately before the read/write operation, and for setting the latency to a first fixed value at all times, for the first mode during the testing, and for necessarily generating the refresh immediately after the read/write operation, and for setting the latency to a second fixed value at all times, for the second mode during the testing.

Semiconductor memory device, test circuit and test method

A reader/writer of a wireless communication device transmits a carrier signal from an antenna, and if there is not response from an IC card within a preset time after transmitting the polling command, the carrier signal is temporarily controlled to an OFF state.

Wireless communication device for periodically controlling a carrier wave to establish a good communication state with a communication object

Semiconductor memory device and semiconductor memory device control method

There are provided a voltage level control circuit with a reduced power consumption and a method of controlling the same. When a signal 'A' is in a 'L' level and a signal PL entered from the outside of the voltage level control circuit becomes &#x201c;H&#x201d; level, a latch signal La outputted from a latch () becomes &#x201c;H&#x201d; level, whereby NFETs () turn ON. A voltage dividing circuit comprising resistances () and current mirror differential amplifiers () are placed in active states to output &#x201c;H&#x201d; as a signal A which controls a boost voltage Vbt (word line driving voltage. As the boost voltage Vbt is increased and reaches to a reference voltage Vref, a voltage Vbecomes &#x201c;H&#x201d;, whereby the signal A becomes &#x201c;L&#x201d;. After the signal A become &#x201c;L&#x201d;, the latch () is made through. At this time, the signal PL is &#x201c;L&#x201d;, the latch signal La outputted from the latch () becomes &#x201c;L&#x201d;, whereby the NFETs () turn OFF. As described here, the NFETs () is kept OFF in the other time period than when needed, in order to reduce the power consumption.

Growing community of inventors

Tokyo, Japan

Atsushi Nakagawa