Hitachi, Ltd.

Hitachi Denshi Kabushiki Kaisha

Atsushi Mizuno

Yasuyuki Kozima

Yukihito Ishihara

In a synchronizing circuit, such as a DPLL (Digital Phase-Locked Loop), adapted to be synchronized in accordance with clock signals of an external clock, a programmable timer in the circuit is forcedly reset in synchronism with the edge of an external clock signal pulse at the time of the clock signal's initial state in accordance with a clock detection circuit. Subsequently, baud timing of the external clock signals is detected by making use of internal clock signals produced by the circuit. Synchronism is thus established and maintained between the circuit and the external device.

Growing community of inventors

Kodaira, Japan

Atsushi Mizuno