Fujitsu Corporation

Socionext Inc.

Fujitsu Microelectronics Limited

Fujitsu Semiconductor Limited

Atsushi Matsuda

Tachio Yuasa

Kunihiko Gotoh

Osamu Kobayashi

Yuji Segawa

Win Chaivipas

Masashi Okubo

Tohru Mizutani

Kenichi Minobe

Hirokazu Tanaka

Hiromi Nanba

Shigeaki Kawai

Akira Haga

Yoshinori Yoshikawa

Atsushi Hitaka

Kenichi Kodato

A level shifting circuit includes a first inverter, a second inverter, and a third inverter which are connected in a cascade. The first inverter operates at a first power supply voltage supplied to a first power supply line, and the third inverter operates at a second power supply supplied to a second power supply line. The second inverter includes a first p-type transistor having a source connected to the first power supply line, a second p-type transistor having a source connected to the second power supply line, and a first n-type transistor having a source connected to a ground line. Each gate of the first and second p-type transistors and the first n-type transistor is connected to an output terminal of the first inverter, and each drain of the first and second p-type transistors and the first n-type transistor is connected to an input terminal of the third inverter.

Level shifting circuit and integrated circuit

A first tuning circuit tunes an oscillation frequency by changing, based on a first control signal, capacitance values of variable capacitive elements connected in parallel to an inductor. A second tuning circuit switches capacitive elements in and out of parallel connection with the inductor by turning on and off a transistor based on a second control signal, to thereby tune the oscillation frequency. A switching circuit includes n-channel transistors whose drains are connected via resistor elements to the source or drain of the transistor and a power and whose sources are grounded, and changes a bias voltage of the second tuning circuit by turning on and off the n-channel transistors based on the second control signal.

Voltage controlled oscillator and PLL circuit

A frequency division correction circuit includes: a first frequency divider configured to perform decimal frequency division on an input signal and output a first frequency division signal and a second frequency division signal which are different from each other in duty ratio; and a corrector configured to generate a first output signal having an intermediate duty ratio between a duty ratio of the first frequency division signal and a duty ratio of the second frequency division signal on the basis of the first frequency division signal and the second frequency division signal.

Frequency division correction circuit, reception circuit, and integrated circuit

A timing adjustment circuit includes a voltage-controlled delay line, a phase detector, a control voltage generation circuit, and a startup circuit. The voltage-controlled delay line receives an input clock signal and generates multi-phase clocks, a delay amount of each of the multi-phase clocks is changed according to a control voltage. The phase detector detects a phase difference between a first clock and a second clock, the first clock is a reference, the second clock is generated from the voltage-controlled delay line. The control voltage generation circuit generates the control voltage on the basis of the detected phase difference. The startup circuit operates for a certain period after activation, and continuously changes the control voltage between a first voltage and a second voltage.

Timing adjustment circuit and semiconductor integrated circuit device

An ADPLL includes a digital controlled oscillator, a first counter counting a number of clocks from the digital controlled oscillator, a second counter to count a multiplication number representing a number of the clocks in a reference clock, a TDC detecting a delayed amount of a phase of the clocks against a phase of the reference clock, an adder adding the delayed amount to a difference between the multiplication number and the number of clocks, a slew rate setting part setting a slew rate of the clocks, an ADC receiving the clocks to which the slew rate is set, a switching part switching between an output of the adder and an output of the ADC, and a controller controlling the slew rate by shifting a phase of the clocks to set a slew rate while the ADLL is locked by utilizing the TDC.

ADPLL

A first switching unit configured to switch a first state for inputting a first clock signal input from a first input terminal, and a second state for inputting an output signal of a second delay element, to a first delay element. A second switching unit configured to switch a first state for inputting a second clock signal input from a second input terminal, and a second state for inputting an output signal of a first delay element, to a second delay element. After the two clock signals are respectively taken in the first delay elements and the second delay elements by putting the first and second switching units into the first state, the control unit puts the first and second switching units into the second state. An output unit outputs a phase difference obtained by decoding values stored in FFs in the second state.

Time-to-digital converter and control method

A clock generating circuit includes: a counter that counts a number of pulses of an oscillation clock signal existed within one cycle of a reference clock signal; a first time-to-digital converter that generates a plurality of phases of first clock signals by delaying the oscillation clock signal; a second time-to-digital converter that generates a plurality of phases of second clock signals by delaying the oscillation clock signal by a short delay time; a third time-to-digital converter that generates a plurality of phases of third clock signals by delaying the delayed first clock signal; a delay control unit that outputs a delay control signal based on a difference between a cycle of the oscillation clock signal and a target cycle; and an oscillator that generates, based on a cycle of the reference clock signal, the oscillation clock signal whose cycle is 1/m of the cycle of the reference clock signal.

Clock generating circuit

A TDC circuit include: a first delay circuit having first inverting delay devices connected to form a loop, the first inverting delay devices outputting a inverted signal according to an input signal after a first signal delay period; a second delay circuit having second inverting delay devices connected to form a loop, the second inverting delay according to an input signal after a second signal delay period different from the first signal delay period; first flip-flop circuits that latch the logical values of third pulse signals including the first pulse signal output from the first inverting delay devices based on fourth pulse signals including the second pulse signal or pulse signals; a first counter that counts the third pulse signal; a second counter that counts the fourth pulse signal; and a detection result output circuit that stores the count from the first counter and the count from the second counter.

Time-to-digital converter

A clock generator includes a digitally controlled oscillator configured to generate an output clock having a frequency depending on an input code; a phase comparison section configured to output a phase difference signal by comparing a reference phase with a phase of the output clock, the reference phase being based on an input clock and a predetermined frequency multiplication number; a low-pass filter configured to provide the input code for the digitally controlled oscillator by filtering the phase difference signal; a waveform generating section configured to generate a predetermined spread spectrum wave, the predetermined spread spectrum wave being to be added with both of the frequency multiplication number and the input code; and a detection/compensation section configured to compensate the input code so that the phase difference is reduced, the phase difference being detected from the phase difference signal.

Clock generator and system including the same

A PLL circuit includes: a first counter to accumulate a frequency command word in response to a reference clock signal and to generate a first counted value; a second counter to count an output clock signal and generate a second counted value; a time measuring circuit to measure an interval between a transition edge of the reference clock signal and a transition edge of the output clock signal to output a third counted value; a phase difference normalizing circuit to multiply the third counted value by a normalizing coefficient to generate a first phase difference; an operating circuit to subtract a value obtained by subtracting the first phase difference from the second counted value from the first counted value to generate a phase difference signal; and an oscillator to change a frequency of the output clock signal based on the phase difference signal.

PLL circuit, method for operating PLL circuit and system

A PLL circuit has a phase comparator to receive an input signal and a feedback signal, a charge pump controlled by an output of the phase comparator, a lowpass filter part to receive an output of the charge pump, a current controlled oscillator controlled by an output of the lowpass filter part, and a frequency divider to frequency-divide an output of the current controlled oscillator and to output the feedback signal. The lowpass filter part has an amplifier to receive the output of the charge pump and a reference voltage, and a circuit part including capacitors and resistors to receive the output of the charge pump and an output of the amplifier.

PLL circuit and semiconductor device

A semiconductor device includes a first analog circuit () adapted to a first performance, and a second analog circuit () realizing a second performance higher than the first performance by cooperating with the first analog circuit. It becomes possible to switch circuit characteristics appropriately in accordance with a requested performance while suppressing an increase of a circuit scale, by operating the first analog circuit and interrupting a power supply to the second analog circuit when the first performance is requested, and by operating the first analog circuit and the second analog circuit together when the second performance is requested to thereby share the first analog circuit.

Semiconductor device, radio terminal device, and radio communication equipment

A band gap reference circuit is configured by connecting an emitter of a transistor, having the base and the collector thereof grounded, to an internal circuit, and by connecting an emitter of another transistor, having the base and the collector thereof grounded, to the internal circuit via a resistor having a positive temperature dependence with respect to the absolute temperature, so as to ensure that a constant output current with a small temperature dependence can be generated, without providing any voltage-current conversion circuit and without generating a constant output voltage, while suppressing expansion in the circuit scale but based on a circuit configuration allowing lowering in the power source voltage.

Semiconductor circuit with positive temperature dependence resistor

A D/A converter in which reference voltage around which voltages outputted vary is not generated by an amplifier in order to reduce electric current consumption. A resistor circuit divides power supply voltage and outputs a plurality of voltages which make up an arithmetic progression. A decoder circuit decodes a digital signal and outputs a control signal. A switching circuit is turned on/off in accordance with the control signal sent from the decoder circuit and selects and outputs one of the plurality of voltages outputted from the resistor circuit. In a conversion circuit, a voltage equal to half of the power supply voltage is obtained by dividing the power supply voltage by resistors and inputted to an inverting input terminal of an operational amplifier which forms a non-inverting amplifier, and the voltage inputted from a switching circuit to a non-inverting input terminal of the operational amplifier is converted into a voltage which varies around a voltage equal to half of the power supply voltage and the converted voltage is outputted. As a result, there is no need to use an amplifier for outputting the voltage equal to half of the power supply voltage and electric current consumption can be reduced.

D/A converter and semiconductor device

An integrated circuit includes an analog signal output unit which converts a digital output signal into at least one analog output signal, and outputs the at least one analog output signal, an analog signal input unit which converts at least one analog input signal received from an exterior into a digital input signal, a switch circuit which provides at least one signal path through which the at least one analog output signal is supplied from the analog signal output unit to the analog signal input unit as the at least one analog input signal, and an offset adjustment control circuit which supplies an output offset from the analog signal output unit to the analog signal input unit via the at least one signal path so as to detect the digital input signal inclusive of the output offset and an input offset, and cancels offsets of the analog signal output unit and the analog signal input unit in response to the output offset and the input offset obtained from the detected digital input signal.

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Akishima, Japan

Atsushi Matsuda