Kabushiki Kaisha Toshiba

Alps Electric Co., Ltd.

Toshiba Electronic Devices & Storage Corporation

Sony Corporation

Fuji Xerox Co., Ltd.

Taiyo Yuden Co., Ltd.

Sony Group Corporation

Alps Alpine Co., Ltd.

Atsushi Masuda

Masatoshi Sekine

Ryuji Hada

Atsushi Mizuno

Hiroaki Nishi

Kazuyoshi Kohno

Shigeru Furuki

Keiichi Nashimoto

Yutaka Ota

Yoshinori Shigeta

Ryuichiro Ohyama

Kazuhiko Hiratsuka

Yukihito Oowaki

Hideo Shimizu

Kazunori Ohuchi

Hiroyuki Bannai

Masao Ohkita

Takehisa Kato

Shinji Ishikawa

Toru Sawada

Shinichi Sasaki

Tomokuni Wauke

Takeshi Kitahara

Naho Suzuki

Yohei Sakuraba

Kunihiko Gunji

Hiroshige Fujii

Osamu Shigenai

Naoki Endo

Takahiro Kawauchi

Takamichi Fuke

Takahiro Endo

Masami Aihara

Shinichi Omori

Takeshi Harano

Tsutomu Takei

Yuuji Hirasawa

Takanao Amatsubo

I Ka

Masayuki Yoshii

Hiroki Tagawa

Jeffery P Hansen

Kazuyoshi Ozawa

Marcello Milli

Eiji Chihara

Junsei Abe

Atsushi Ozoe

Shinji Fujimura

To provide an audio processing device including a configuration in which a different microphone is used for generation of directivity depending on a frequency band.

Audio processing device having microphones arranged with different spacing and diameters

An image processing apparatus in an embodiment includes a FIFO memory, a plurality of line buffers, an image processing circuit, and a control circuit. The plurality of line buffers store data inputted from a plurality of cameras. The image processing circuit performs predetermined image processing on the data stored in the plurality of line buffers. The control circuit performs control, according to an output control signal, such that output of data to the plurality of line buffers is stopped and the data stopped from being outputted is stored in the FIFO memory.

Image processing apparatus

An image processing apparatus according to an embodiment includes a preprocessing circuit and a distortion correction circuit configured to process, in a time division manner, a plurality of images generated by a plurality of image pickup units and an output buffer circuit configured to buffer the processed plurality of images in a unit of a block and add an identification tag including an address and an identification ID to the block.

Image processing apparatus and image processing method

An image processing apparatus includes first and second line buffers, an image processing circuit configured to perform an image processing on first pixel data stored in the first line buffer and then second pixel data stored in the second line buffer, and a controller configured to control writing of the second pixel data in the second line buffer at a timing aligned with a synchronizing signal and reading of the second pixel data written in the second line buffer for the image processing by the image processing circuit at a timing of a completion of the image processing by the image processing circuit of the first pixel data stored in the first line buffer.

Image processing apparatus, image processing method, and image processing program

The image processing device of an embodiment, to which multiple inputted pixels forming an inputted image are inputted in a raster scan order, includes a written pixel position calculating circuit configured to convert the position of each of the inputted pixels to a first pixel position in an outputted image, a read-out pixel position calculating circuit configured to convert the position of an outputted pixel near the first pixel position in the outputted image to a second pixel position in the inputted image, and a pixel interpolating circuit configured to calculate the pixel value of the second pixel position through interpolation with surrounding pixels in the inputted image.

Image processing device and image processing method

An in-vehicle input device includes a touch panel including a lower electrode, an upper electrode, and a spacer, and is capable of detecting a capacitance between the lower electrode and the upper electrode. The device has an operation surface located above the upper electrode. The operation surface includes a plurality of operation areas. The spacer has a plurality of openings that coincide with the operation areas in plan view. The device further includes a suppression layer that is disposed between the operation surface and the upper electrode or disposed on an upper surface of the operation surface. The suppression layer eliminates or reduces formation of a capacitance between the upper electrode and an operator. The device detects an input operation based on a change in distance between the lower electrode and the upper electrode in response to pressing any of the operation areas by the operator.

In-vehicle input device

Provided is an image processing apparatus including a distance information acquisition unit that acquires distance information on a distance up to an object imaged by an image sensor, a pixel value information acquisition unit that acquires pixel value information of an image corresponding to the object, and a tracking unit that tracks the object that moves, based on the acquired distance information and the acquired pixel value information.

Object tracking based on distance prediction

In an embodiment, a capacitor bodyof a multilayer ceramic capacitorsuccessively has a high-capacitance part CPand a low-capacitance part CPin the height direction, sharing one common internal electrode layeramong 30 internal electrode layers. The high-capacitance part CPincludes 23 internal electrode layers-and one common internal electrode layer, while the low-capacitance part CPincludes one common internal electrode layerand six internal electrode layers-, where the facing distance FIof the seven internal electrode layersand-included in the low-capacitance part CPis wider than the facing distance FIof the 24 internal electrode layers-andincluded in the high-capacitance part CP. The multilayer ceramic is capacitor capable of suppressing noise that may otherwise generate in a mounted state, while also reducing ESL in high-frequency ranges of several hundred MHz or higher.

Multilayer ceramic capacitor

An input device includes: an operation portion allowing an input operation by an operating body contacting with or coming close to an upper surface thereof; an input detection portion detecting an input operation with respect to the operation portion; a driving member provided below the operation portion and driving the operation portion in an up-down direction; an elastic member provided below the operation portion; a case member holding the driving member; an interlocking member provided below the operation portion, connected to the operation portion, and driven with the operation portion; a restricting member provided between the operation portion and the interlocking member and restricting upward movement of the interlocking member; and an elastic first damper member provided below the interlocking member and contactable with the interlocking member. The elastic member elastically urges the interlocking member such that the interlocking member is brought into press contact with the first damper member.

Input device

An apparatus includes a display control section configured to control display of image data for an image, the image data including flash reach information identifying at least one portion of the image corresponding to at least one region reached by light from a flash. Also described are a method and computer-readable storage medium for controlling display of image data for the image.

Image display using flash reach information

A high-level synthesis apparatus for automatically generating a register transfer level (RTL) logic circuit from a behavioral description has a scheduling unit configured to perform data flow analysis and scheduling to generate a data flow graph showing an operation cycle of an operation from the behavioral description, a scheduling result inputting/outputting unit configured to extract a point to be allocated to a register from the data flow graph and output register information indicating the point, the scheduling result inputting/outputting unit being provided with dynamic analysis data that includes at least one of the number of times that data at the point has been substituted and the number of times that a value stored at the point has changed by a predetermined simulation, an allocating unit configured to consult dynamic analysis data and allocate circuit elements to the behavioral description, and an RTL description generating unit configured to generate the logic circuit based on the allocation of circuit elements by the allocating unit.

High-level synthesis apparatus, high-level synthesis system and high-level synthesis method

A design apparatus for designing a processor re-configurable for an application, includes an analysis unit that analyzes the content of a program to be executed by the processor; a hardware extension unit that searches the program for a part of the program allowing hardware extension in accordance with the analysis results by the analysis unit and generates hardware extension information for the searched part; an extended instruction definition unit that searches the program for a part allowing use of an extended instruction in accordance with the analysis results by the analysis unit and generates definition of an extended instruction for the searched part; and a performance estimation unit that estimates whether or not the performance of the processor satisfies a target performance using at least one of the hardware extension information generated by the hardware extension unit and the definition of the extended instruction generated by the extended instruction definition unit.

Program segment searching for extension instruction determination to design a processor that meets performance goal

A data processing system includes a block setting module setting a to-be-processed block shape including subject data, which is one of 2-dimentional data in a matrix stored in a virtual storage area, and influenced data influenced by results of processing subject data, a division module dividing 2-dimentional data into a plurality of execution blocks based on information of the to-be processed block shape, and a processing module sequentially processing data in each execution block along a row direction in units of execution blocks.

Data processing system and method for 2-dimensional data with setting a block shape

A design apparatus for designing a configurable processor for an application, includes an analysis unit that analyzes the content of a program to be executed by the processor; a hardware extension unit that searches the program for a part of the program allowing hardware extension in accordance with the analysis results by the analysis unit and generates hardware extension information for the searched part; an extension instruction definition unit that searches the program for a part allowing use of an extension instruction in accordance with the analysis results by the analysis unit and generates definition of an extension instruction for the searched part; and a performance estimation unit that estimates whether or not the performance of the processor satisfies a target performance using at least one of the hardware extension information generated by the hardware extension unit and the definition of the extension instruction generated by the extension instruction definition unit.

Designing configurable processor with hardware extension for instruction extension to replace searched slow block of instructions

An apparatus for designing a semiconductor integrated circuit having a configurable processor includes: a software information storage section storing software information including software descriptions; a hardware information storage section storing hardware information including hardware descriptions of the semiconductor integrated circuit; a processor information storage section storing processor information; a hardware implementation specification section specifying an algorithm of a portion to be implemented by hardware from among the software descriptions; a hardware changing section generating hardware descriptions from the algorithm of the specified portion, and changing the hardware information and the processor information; a software changing section generating software descriptions in which the algorithm of the specified portion is replaced with an algorithm for controlling the implemented hardware, and changing the software information; and a performance analyzer analyzing a performance of the semiconductor integrated circuit based on the changed software information, the changed hardware information and the changed processor information.

Apparatus, method and program for designing semiconductor integrated circuit

Growing community of inventors

Tokyo, Japan

Atsushi Masuda