Kabushiki Kaisha Toshiba

Atsushi Kurobe

Naoharu Sugiyama

Tsutomu Tezuka

Shinichi Takagi

Tomohisa Mizuno

Hideto Furuyama

Mitsuhiro Kushibe

Tetsuo Sadamasa

Shinya Nunoue

Shinobu Fujita

Tetsufumi Tanamoto

Yoshiko Hiraoka

Riichi Katoh

Yoshito Kawakyu

Seiji Imai

Yoshita Kawakyu

Paul W McIlroy

Tohru Nishibe

A semiconductor device comprises a base substrate, a silicon oxide layer formed on the base substrate, a first semiconductor layer formed on the silicon oxide layer, the first semiconductor layer including an SiGe layer with a Ge concentration not less than 30 atomic %, a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer including a Ge layer or an SiGe layer with a Ge concentration higher than the first semiconductor layer, a gate electrode configured to induce a channel in a surface region of the second semiconductor layer, and a gate insulating film formed between the second semiconductor layer and the gate electrode.

Semiconductor device and method of manufacturing substrate

Method of manufacturing a substrate using an SiGe layer

A method of manufacturing a semiconductor device comprising the steps of forming a first crystal silicon layer doped with oxygen on a single crystal silicon substrate, forming a crystal silicon-germanium layer on the first crystal silicon layer, forming a second crystal silicon layer on the crystal silicon-germanium layer, and imparting strain to the second crystal silicon layer by a thermal treatment.

Semiconductor device and method for manufacturing the same

The invention is intended to form, on an insulating layer, a thin SiGe layer serving as an underlying layer for obtaining a strained silicon layer, and to provide a satisfactory strained Si layer. A SiGe layer,is formed on a Si substrate,and an oxygen ion implantation is effected with ensuring the detainment within the layer thickness of the SiGe layer,. The SiGe layer,is lattice-relaxed by a heat treatment and a buried insulating layer,is formed simultaneously in the SiGe layer,. A strained Si layer,is re-grown on the lattice-relaxed SiGe layer

Semiconductor devices and methods for producing semiconductor devices

A semiconductor device includes a superlattice having a first semiconductor layer having a first band-gap, a second semiconductor layer having a band-gap narrower than the first band-gap, the superlattice having a band structure with an energy level of a conduction band of the second semiconductor layer being lower than an energy level of a conduction band of the first semiconductor layer and an energy level of a valence band of the second semiconductor layer being lower than an energy level of a valence band of the first semiconductor layer, or a band structure with an energy level of a conduction band of the second semiconductor layer being higher than an energy level of a conduction band of the first semiconductor layer and an energy level of a valence band of the second semiconductor layer being lower than an energy level of a valence band of the first semiconductor layer, an exposed face formed on a plane different from a plane orientation on which the superlattice is formed, an end face of the superlattice being exposed to the exposed face, and a channel being formed on the exposed face.

Semiconductor device and memory device

A device structure provides improved efficiency of light emission from a light emitting element made of silicon while rendering such emission electrically controllable. Silicon in the light emitting element comprises fine microcrystals, which are miniaturized sufficiently to cause a quantum size effect. The microcrystals may be 10 nanometers (nm) or less in grain size. A dielectric film of 5 nm thick or less is formed containing therein such microcrystals. The microcrystal structure section is disposed between p- and n-type semiconductor layers. These layers are brought into electrical contact with the microcrystal structure only, while causing the remaining portions to be electrically insulative by a dielectric film or the like. Elementary particles of the opposite polarities, e.g. electrons and holes, are injected by tunnel effect into the microcrystals resulting in emission of light rays with increased efficiency.

Light emitting semiconductor device using nanocrystals

The semiconductor device comprises a first insulating layer formed on the semiconductor substrate, at least one double-deck semiconductor nanocrystal formed on the first insulating layer, the at least one double-deck semiconductor nanocrystal comprising a first semiconductor nanocrystal and a second semiconductor nanocrystal stacked one upon the other via a second insulating layer, and a third insulating layer selectively formed on the first insulating layer so as to cover the at least one double-deck semiconductor nanocrystal.

Semiconductor memory device having multilayer group IV nanocrystal

A channel layer and a spacer layer form a heterojunction therebetween. A V-shaped groove is formed in the spacer layer. The sharp bottom of the V-shaped is located above the heterojunction interface. On the bottom of the V-shaped groove a plurality of quantum dots are formed in a line and discretely. A gate electrode is formed above the quantum dots. A source electrode is connected to the heterojunction interface to form an ohmic contact therebetween. A drain electrode is connected to the heterojunction interface to form an ohmic contact therebetween. The quantum dots are arranged between the source and drain electrodes.

Quantum dot memory cell

A semiconductor device comprises a semiconductor substrate, a first semiconductor layer under compressive strain formed on the semiconductor substrate, a p-type MISFET (Metal Insulator Semiconductor Field Effect Transistor) formed in a predetermined region of the first semiconductor layer, a second semiconductor layer in a lattice-relaxation condition formed on the first semiconductor layer in a region other than the predetermined region with an insulating film lying therebetween, wherein the insulating film has an opening and the first and second semiconductor layers are connected through the opening, a third semiconductor layer under tensile strain formed on the second semiconductor layer, and an n-type MISFET (Metal Insulator Semiconductor Field Effect Transistor) formed in the third semiconductor layer.

Si-SiGe semiconductor device and method of fabricating the same

A microcavity semiconductor laser disclosed therein includes a double-heterostructure section including an intermediate active layer sandwiched between a first or lower cladding layer and a second or upper cladding layer above a semiconductive substrate. A first multi-layered reflector section is arranged between the substrate and the double-heterostructure section to have its reflectance which becomes maximum near the oscillation wavelength of the laser. The upper cladding layer is semi-spherically formed. A three-dimensional optical reflector covers the double-heterostructure section, for controlling spontaneous emission obtained in the double-heterostructure section along various directions, and for increasing the coupling ratio of spontaneous emission with a specific laser mode, thereby to decrease the threshold current.

Semiconductor laser device with multi-directional reflector arranged

The present invention provides a dry etching method, having the steps of introducing a mixed gas consisting of a reactive gas and an inert gas into a plasma chamber for generating a plasma, with the partial pressure of each of these gas components being controlled, exciting the mixed gas within the plasma chamber so as to generate ionized particles and excited particles having high reactivity, withdrawing the particles generated in the plasma chamber into a sample chamber having a compound semiconductor substrate housed therein, and physically and chemically etching the compound semiconductor substrate with the particles.

Dry etching method

In an embedded type semiconductor laser, at least three layers of a first conduction type clad layer, a quantum well active layer which contains a first or second conduction type or a pn junction, and a second conduction type clad layer, are grown successively on a first conduction type substrate. A high concentration impurity doped layer is provided excluding a predetermined striped region, situated adjacent to the active layer. An impurity diffusion is carried out by heat treatment which diffuses dopant from the high concentration impurity doped layer to the active layer.

Method of manufacturing an embedded type semiconductor laser

In a carrier injection type light emitting semiconductor device with a QW structure, a p-type impurity doped layer and/or an n-type impurity doped layer are inserted into an optical wave guide layer so as to cancel an internal electric field in an active region.

Growing community of inventors

Yamato, Japan

Atsushi Kurobe