Hitachi Micro Systems, Inc.

Atsushi Kiuchi

Richard W Blasco

Chandravadan N Patel

Hiromitsu Inada

A device for multi-precision and block arithmetic support in a digital processor including a multiplier for multiplying two signed, unsigned or signed and unsigned binary numbers and having a dynamic range greater than -1 to +1, an arithmetic and logic unit for performing arithmetic and logic operations, a barrel shifter for barrel shifting at least one binary number, shifters for selectively shifting the output of the multiplier and multiplexers for selecting and interconnecting the outputs and inputs of the multiplier, the arithmetic and logic unit, the barrel shifter and the shifters.

Device for multi-precision and block arithmetic support in digital

A digital peak and valley detector including a peak value address register, a valley value address register, a peak value data register, a valley value data register, a peak comparator for comparing the value stored in the peak value data register with value data contained in the digital signal applied to the digital peak and valley detector and for causing the greater of the two to be stored in the peak value data register while simultaneously storing the address in the peak value address register and a valley comparator for comparing the valley value contained in the valley value data register with the value data contained in the digital signal applied to the digital peak and valley detector for determining which is less and for causing the value and the address of the smaller of the two to be stored respectively in the valley value data and the valley value address registers.

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Tokyo, Japan

Atsushi Kiuchi