Hitachi Ulsi Systems Co., Ltd.

Atsushi Kishihara

Katsuyoshi Tanaka

In a configuration where a main control unit and various peripheral modules are bus-connected on a communication line, the communication line includes a control line in addition to signal lines serving as a differential pair. The control line is, for example, a bus of the logical AND. When the main control unit drives the control line to a 'L' level for a certain period of time or more, the peripheral modules detect that and carry out a hardware reset for itself. When the main control unit issues a command to output a value of a particular bit of own identification number to the peripheral modules via the signal lines, the peripheral modules output the result to the control line, and the control line performs an AND operation. By utilizing the AND operation result, automatic address allocation to the peripheral modules is carried out.

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Kokubunji, Japan

Atsushi Kishihara