Juniper Networks, Inc.

Sun Microsystems, Inc.

Jeda Technologies, Inc.

Atsushi Kasuya

Dennis C Ferguson

Hann-Hwan Ju

Gerald Cheung

Devereaux C Chen

Jianzhou Zhao

Baodong Yu

Junying James Yu

Hasan F Ugurdag

Chaoji Li

A network device includes an input interface, at least one processing path and an output interface. The input interface receives data units on a plurality of streams and assigns a first sequence number to each of the received data units. The at least one processing path performs a route look-up for each of the data units, where the route look-up determines a routing destination for a respective data unit. The output interface assigns a second sequence number to each of the processed data units based on a number of memory references associated with the route look-up for each of the data units and re-orders the processed data units based on the second sequence number assigned to each of the processed data units.

Systems and methods for re-ordering data in distributed data forwarding

A network device includes at least one input interface, at least one processing path and at least one output interface. The at least one input interface receives data blocks from a plurality of streams in a first order. The at least one processing path processes each of the data blocks, the processing including performing one or more route look-ups for each of the data blocks. The at least one output interface re-orders the data blocks based on a number of the one or more route look-ups associated with each of the data blocks.

Systems and methods for distributed data forwarding

A system and a method for thread creation where only copied threads share the same stack location for execution, so unrelated threads have individual stack space and can be executed concurrently in multi-processor system. Also, the copy operation of the stack frame is only necessary among the copied threads, so the speed of context switching among individual threads is fast. This operation can be a simple page table modification in the virtual memory management mechanism for further speed up.

System and method for thread creation and memory management in an object-oriented programming environment

Evaluation information of a temporal description is displayed by: structuring data structures into a logical tree structure that is representative of the hierarchy of the temporal expressions, with each tree node representing a temporal primitive operator, and a unique index assigned to each primitive; evaluating the temporal expression, and recording the evaluation trace information that contains the corresponding unique index to the primitive node, the evaluation time stamp, and other information of the evaluation; and selectively displaying an evaluation sequence of the selected result at any level, including from the top of the tree structure of the temporal evaluation in order to show the evaluation history of the selected result at a lower level of the expression tree, where the selection methods include a graphical interface on the screen to select a child expression at a given tree level.

Evaluation and display of temporal descriptions

An electronic circuit verification system and method includes an HDL circuit simulator and a circuit simulation verifier that pass control back and forth between each other, and that cooperate so as to perform circuit verification tasks than would be very difficult to perform using only the HDL circuit simulator. The circuit simulation verifier executes a test bench so as to define operational correctness and/or performance criteria, including at least one Expect Event, each Expect Event comprising a combination of one or more signal values that are expected to occur during simulation, and a time frame during which the signal value combination is expected to occur. The circuit simulation verifier includes instructions for blocking execution of a thread of execution associated with the test bench until the earlier of the combination of one or more signal values occurring during simulation and the time frame expiring.

Verification system for simulator

An electronic circuit verification system and method includes an HDL circuit simulator and a circuit simulation verifier that pass control back and forth between each other, and that cooperate so as to perform circuit verification tasks than would be very difficult to perform using only the HDL circuit simulator. The circuit simulation verifier is coupled to the HDL circuit simulator so as to control the HDL circuit simulator's operation, including specifying conditions under which the HDL circuit simulator is to stop simulation of a specified circuit and specifying input signal waveforms to be used by the HDL circuit simulator. The circuit simulation verifier receives signal waveforms generated by the HDL circuit simulator for specified watched signals. The circuit simulation verifier then determines whether predefined logical combinations of the watched signals meet specified operational correctness and/or performance criteria within specified time frames. A test bench is composed of a sequence of instructions, including instructions indicating when to activate various operational correctness and/or performance criteria, instructions for sending commands to the HDL simulator, and branch or condition instructions for controlling which instructions of the test bench are to be executed. Furthermore, a test bench can include instructions for generating a plurality of distinct threads of execution, each of which is composed of its own sequence of instructions, and furthermore can include instructions for conditionally spawning additional threads of execution when specified combinations of Expect Events are satisfied in specified ones of the threads.

Growing community of inventors

Sunnyvale, CA, United States of America

Atsushi Kasuya