Nippon Telegraph and Telephone Public Corporation

Fujitsu Corporation

Hitachi, Ltd.

Nippon Electric Co., Ltd.

Atsushi Iwata

Seiji Kato

Norio Ueno

Akihiko Ito

Yukio Akazawa

Yasuyuki Matsuya

Takashi Kimura

Kenji Maio

Junichi Takahashi

Mitsuo Kakuishi

Takashi Matsuura

Norio Yokozawa

Akinori Shibayama

Hiroyuki Kikuchi

Minpei Fujinami

Kenji Fujikata

Tadahiro Saito

Hirokazu Fukui

Takao Kaneko

Sanshiro Hattori

Yoshiharu Shigeta

An information processing device includes: a processing circuit that processes information; a management circuit that is independent of the processing circuit and that performs status management of hardware including the processing circuit; and a memory into which the management circuit stores setting information of the management circuit and from which the management circuit extracts setting information of the management circuit, the memory being physically connectable to and removable from the management circuit.

Apparatus for restoring setting information of a board management controller from a backup memory before loading an OS when a system board is replaced

An array processor comprising multiplexers, plural processing elements connected through the multiplexers in the form of a ring and a control unit for controlling the multiplexers and the processing elements. Each of the processing elements is connected to an input vector data bus via the multiplexer and directly to an I/O data bus, so that two types of input vector data are inputted to the processing element simultaneously. Flags indicating a position of respective vector data are added to each one of input vector data, series composed of a combination of plural types of input vector data series. The processing element judges a processing status of the processing element to control a selection of the input vector data bus or the transfer path, data transfer between the processing elements, or data input/output to/from the I/O bus, so that the overall array processor executes autonomous control of all the combinations of the vector data of the two types of input vector data series. The array processor realizes parallel processing of pattern matching computation based upon dynamic time warping with a high efficiency and thus realizes a highefficiency utilization of hardware resources including processing elements and network.

Array processor and control method thereof

The frequency divider includes a first or prescaling counter which selects between first and second frequency division factors, in response to a first control signal, and then divides an input signal frequency responsive to the first control signal. A second and programmable counter frequency divides the output of the first or prescaling counter by a third frequency-division factor. A third and programmable counter frequency divides the output of the first counter by a fourth frequency-division factor which is smaller than the third frequency-division factor. A switching control circuit then converts the output of the third counter and supplies the converted signal to the first counter, as the first control signal. The digital frequency divider is suitable for use a part of a phase-locked loop frequency synthesizer.

Digital frequency divider suitable for a frequency synthesizer

A phase-locked loop circuit provides a phase comparator which receives input signals through a first input terminal, a loop filter which receives a first output and a second output of the phase comparator, and a voltage-controlled oscillator which produces output signals of an oscillation frequency proportional to the first output and the second output of the loop filter. The signals corresponding to the output signals produced by the voltage-controlled oscillator are supplied to a second input terminal of the phase comparator so that the phase of the signals supplied to the first input terminal of the phase comparator is compared with the phase of the signals supplied to the second input terminal. In the present invention, the loop filter comprises a first capacitor connected to the output terminal of the loop filter, second and third capacitors, each having a terminal connected to the output terminal of the loop filter, and a charging circuit for electrically charging the first, second, and third capacitors. The charging circuit is connected in parallel with the second capacitor. A discharging circuit for discharging the first, second, and third capacitors is connected in parallel with the third capacitor.

Phase-locked loop using integrated switched filter

The analog output from a local DAC comprising an LDAC and an MDAC, in which the full scale of the LDAC is always larger than the quantized level of the MDAC, is compared with an input analog signal which is sampled and held. A digital code obtained by successive approximation in accordance with the result of the comparison is stored in a successive approximation register. A shift code for calibrating the D/A conversion in the local DAC by shifting the digital code which is previously allotted to each digital code is stored in a shift code generating circuit (ROM). The digital code from the successive approximation register is digitally shifted in accordance with the shift code by a code shift circuit such as a digital adder/subtractor to obtain an A/D conversion output. An analog to digital converter with a high accuracy and an improved conversion speed is inexpensively fabricated in the form of a one chip LSI by a usual CMOS process.

Analog to digital converter

A digital to analog converter comprising a first digital to analog converter for generating an output signal of higher order bits; a second digital to analog converter for generating a full scale output as an output signal of lower order bits which is always larger than the output value (1 LSB) corresponding to one bit of a digital input at the least significant bit of the first digital to analog converter; adding means for adding the output signal from the first digital to analog converter to the output signal from the second digital to analog converter to form an analog output signal; and a code converter for applying to the first and second digital to analog converters an input code obtained by shifting a digital input signal applied to the first and second digital to analog converters by a given value such that the relationship between the digital input signal and the analog output signal is made substantially linear.

Digital to analog converter

A switched capacitor filter having at its input, a signal converter for creating so-called 100% sample and hold signals. The signal converter comprises a plurality of switched capacitors. The switched capacitors, connected in parallel with each other, receive the same successive input signals and supply the so-called 100% sample and hold input signals to the switched-capacitor filter. The switched capacitors, on one hand, charge each of said input signals sequentially and, on the other hand, alternately discharge the respective stored input signals one by one.

Switched-capacitor filter

A switched-capacitor filter provided with, at its input stage, a prefilter comprised only of a plurality of additional switched capacitors together with a switched capacitor common to the switched-capacitor filter. The switched capacitor common to the switched-capacitor filter is driven by primary clock pulses having a period T, while the additional switched capacitors are sequentially driven by secondary clock pulse groups. Each of the secondary clock pulse groups has the same period T, and the phases of the second clock pulse groups are shifted by T/2.sup.k, 2T/2.sup.k, 3T/2.sup.k . . . (2.sup.k -1)T/2.sup.k with respect to the first clock pulses (k is a positive integer). The sampled and held signals in the switched capacitors are supplied synchronously to the switched-capacitor filter.

An electron beam deflection control system includes a first signal generation circuit which generates a triangular signal varying at a comparatively low speed, a second signal generation circuit which generates a stepped signal varying at a comparatively high speed, and a switching arrangement to change over the first and second signal generation circuits and to drive one of them, whereby the signal from the generation circuit selected by the switching arrangement is used as a deflection signal for an electron beam.

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Tokorozawa, Japan

Atsushi Iwata