Seiko Epson Corporation

Atsushi Ishikawa

Tsuyoshi Tamura

Hiroaki Nomizo

A circuit apparatusincludes: an interface circuitthat receives setting data; and a control circuitthat controls the operations of the circuit apparatusbased on the setting data and also controls access to a nonvolatile memory. The control circuitgenerates error detection data based on the setting data received by the interface circuit, and writes the setting data and the error detection data to the nonvolatile memory

Circuit apparatus, electro-optical apparatus, electronic device, and mobile unit

An integrated circuit device includes an I/O circuit which buffers and outputs an input signal D from a pad when an enable signal ENB is set at a second voltage level, a circuit block to which an output signal from the I/O circuit is input, and a malfunction prevention circuit which outputs to the circuit block an output signal QP of which a voltage level is set by a first power supply VDDC in a period Tin which the signal ENB is set at a first voltage level and a period Tincluding a period in which the signal ENB changes from the first voltage level to the second voltage level, and outputs to the circuit block the output signal QP corresponding to an output signal QI from the I/O circuit in a period Tin which the signal ENB is set at the second voltage level.

Integrated circuit device and electronic instrument

A shift register includes M (M is an integer larger than two) stages of transfer elements and a control circuit. The M stages of the transfer elements transfer N (M&#x3e;N, N is an integer larger than one) data signals sequentially input within one cycle. To the control circuit, N clock signals and a control signal are input within the one cycle and the control circuit supplies a shift clock signal to N stages of the transfer elements among the M stages of the transfer elements and supplies a skip fixed logic signal to (M&#x2212;N) stages of the transfer elements among the M stages of the transfer elements based on the control signal.

Shift register having skip function, and display driver device, display device and electronic instrument using the same

A semiconductor device, comprising: a first transistor of a second electric conductivity type formed in a substrate including impurities of a first electric conductivity type; and a second transistor of the second electric conductivity type formed in the substrate, a source region of the second transistor being shared with a source region of the first transistor; wherein in a lower layer of a gate insulating film of the first transistor, a first offset layer of the second electric conductivity type is formed adjacent to a channel region of the first transistor, in a lower layer of a gate insulating film of the second transistor, a second offset layer of the second electric conductivity type is formed adjacent to a channel region of the second transistor, and in the source region, a first diffusion layer of the first electric conductivity type and a second diffusion layer of the first electric conductivity type in the upper layer of the first diffusion layer are formed, and wherein the second diffusion layer is provided so as to come in contact with the first and second offset layers via the first diffusion layer, and the impurity concentration of the first diffusion layer is higher than the impurity concentration of the substrate.

Semiconductor device and method for manufacturing the same

The invention provides a semiconductor integrated circuit having a zooming function independently in a driver IC for driving a display device. The semiconductor integrated circuit can be a semiconductor integrated circuit which respectively outputs a plurality of two-dimensional images of different sizes according to a mode signal from a plurality of output terminals. It can include select signal shift circuits and the like which, in a first mode, synchronize with one of a rise-up or a fall of a clock signal and sequentially supply a select signal to each of select signal supply terminals, and, in a second mode, synchronize with the rise-up and the fall of the clock signal and sequentially supply the select signals to two of select signal supply terminals at a time. The invention can also include a first group of latch circuits and the like which hold image data in response to the select signals sequentially supplied to the select signal supply terminals, and a second group of latch circuits and the like which hold image data outputted from the first group of latch circuits in response to a line pulse.

Growing community of inventors

Fujimi, Japan

Atsushi Ishikawa