Fujitsu Corporation

Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Spansion Llc.

Atsushi Ike

Masato Tatsuoka

David Thach

Ryosuke Oishi

Shinya Kuwamura

Shinichiro Tago

Yutaka Tamiya

Seigo Takahashi

Yoshimasa Takebe

Teruhiko Kamigata

A simulation apparatus includes a memory, and a second processor configured to detect an internal state of the first processor in the operation simulation, when a target block in the operation simulation changes, the target block being included in blocks obtained by dividing code of the program, generate association information in which the internal state detected by the detecting section and performance values of instructions included in the target block in the detected internal state are associated with each other, and execute an execution code that allows a performance value when the first processor executes the target block to be calculated based on the association information, by using the internal state detected and the association information generated for the target block, to thereby calculate a performance value when the first processor executes the target block.

Simulation apparatus and storage medium

A computation method includes: obtaining one or more first performance values of one or more instructions in a specific code for each of a plurality of first combinations of behavior result of a cache memory when a plurality of accesses to a memory area are executed; obtaining a second combination of behavior result of the cache memory when the plurality of accesses are executed based on an execution result of behavior simulation of the cache memory for a case where a processor executes a program including the specific code; and computing, by a computer, a third performance value when the processor executes the specific code based on one or more second performance values of the one or more instructions corresponding to the second combination among the one or more first performance values when the second combination is included in the plurality of first combinations.

Computation method for computing performance value when processor executes code, computation apparatus for computing performance value when processor executes code, and computer readable storage medium storing computation program for computing performance value when processor executes code

A simulation apparatus includes: operations of: dividing code of a program in a target processor into blocks; setting an execution result of an externally-dependant instruction depending on an external environment as a prediction result; carrying out function simulation based on the prediction result; calculating an execution time of the externally-dependant instruction according to instruction execution timing information and a function simulation result; generating host code which makes a host processor execute performance simulation based on the function simulation result: correcting the execution time of the externally-dependant instruction based on a delay time of the externally-dependent instruction and a execution time of an instruction executed before or after the externally-dependent function if an execution result of the externally-dependent function when the host processor executes the host code differs from the prediction result; and setting a corrected execution time of the external-dependent instruction as the execution time of the externally-dependant instruction.

Simulation apparatus and simulation method

A code converterof a simulation apparatusdetects, during the execution of a program in a target CPU, an externally dependent instruction affected by the external environment in each of divided blocks, predicts the execution result of the externally dependent instruction, simulates the instruction execution in the predicted result, and generates a host code in which a code for performance simulation is embedded based on the simulation result. A simulation executorperforms performance simulation about instruction execution in the prediction result of the program using the host code, and when the execution result of the externally dependent instruction is different from the setting of the prediction result during the execution, corrects the execution time of the instruction in the prediction result using the execution time of instructions executed before and after the instruction, and the like. A simulation information collectorcollects and outputs performance simulation information.

Simulation apparatus, method and medium

A communication device includes a memory and a processor coupled to the memory. The processor executes a process including calculating an amount of electricity available in a second device while a first communication unit and a second communication unit with each other, determining a first generation unit to be a generation unit, when the amount of electricity thus calculated is smaller than a predetermined amount, out of the first generation unit that generates navigation information based on information acquired by an information acquisition unit and a second generation unit, and controlling the second device so as to stop supplying power to the second generation unit and to output the navigation information generated by the first generation unit when the first generation unit is determined.

Communication device, mobile terminal, medium, information generation method, and system

A correction apparatus includes an acquirer that acquires the execution time of an instruction in a given block among a block group that includes blocks obtained by dividing program code; a detector that detects a first resource group designated by a tail instruction in a preceding block that is executed before the given block and a second resource group designated by a head instruction of the given block; an identifier that identifies a resource common to the first and the second resource groups; a calculator that from the time when the identified resource is used by the head instruction and the time when use of the identified resource by the tail instruction ends, calculates a delay period caused by the preceding block; a corrector that based on the calculated delay period, corrects the acquired execution time; and an output device that outputs the corrected execution time.

Correction apparatus, correction method, and computer product

In the system, an apparatus for collecting trace information provided on a circuit executing a program includes a counter unit which increments a count value for each execution cycle of the program, and a collection unit outputs trace information at a fetching timing of the trace information outputted by the circuit and a count value of the counter unit at the fetching timing. Another apparatus for processing trace information includes a trace information acquisition unit which acquires the trace information added with a count value from a trace information collection apparatus, a sort processing unit which sorts the acquired trace information based on the count value, and a trace information storage unit which store the sorted trace information.

Apparatus for collecting trace information and processing trace information, and method for collecting and processing trace information

A simulation method and apparatus including a restore point setting unit setting restore points in core models for executing threads using parallel processing. The method also includes storing information for reproducing a state the core models at the restore points.

Simulation method and simulation apparatus

An information processing and method include acquiring a trace group indicating instants of time of execution of processing operations and vestiges of contents of the execution, behavior information indicating behaviors of a processor of the arbitrary system, and state information indicating state transitions of an arbitrary hardware device other than the processor. A behavior trace searching unit searches when an arbitrary behavior is specified from behaviors indicated by the behavior information, a state trace searching unit searches when an arbitrary state transition is specified from the state transition indicated by the state information, an associating unit associates, the traces found by the behavior trace searching unit and the traces found by the state trace searching unit according to an instruction and an outputting unit outputs the traces associated by the associating unit as traces for a simulation of the behaviors.

Computer-readable recording medium storing verification support program, information processor, and verification support method

A verification support apparatus and method are provided. The verification support apparatus executing a simulation controlling a communication between a first hardware model in communication with a bus model and adapted to the same first specifications as the bus model, and a second hardware model in communication with the bus model and adapted to second specifications differing from those of the bus model, the apparatus includes a reception unit that receives data based on the second specifications from the second hardware model, a conversion unit that, based on the first specifications, converts the data received by the reception unit into data adapted to the first specifications; and a transmission unit that transmits the data converted by the conversion unit, via the bus model, to a hardware model which is a transmission destination.

Computer-readable recording medium storing verification support program, verification support apparatus, and verification support method for supporting verification of hardware system design including different hardware models

A software/hardware (SW/HW) partitioning and evaluating program allows a computer to perform a procedure of compiling a source code in which a mark is added to a portion to be executed by hardware, a procedure of generating an executable program for a simulator of CPU on a system-on-chip (SoC), a procedure of storing in memory an execution result of the executable program, and a procedure of evaluating an SW/HW partition based on the execution result.

Software/hardware partitioning program and method

A high-speed multicore model simulator is realized. A multicore model simulator having a plurality of threads, and a plurality of core models executing the aforesaid plurality of threads is provided. The plurality of core models are a plurality of processor core models, each of which executes one thread, and they are synchronized with each other every predetermined number of execution instructions of each thread.

Multi-core model simulator

An address translator capable of reducing system loads in address translation and an overhead in switching between operating systems. A plurality of address translation buffers classifies and stores virtual addresses and real addresses based on a plurality of operating systems which is run by a processor. For example, the address translation buffers store the virtual addresses and the real addresses in correspondence with the operating systems. According to a running operating system, an address translation controller accesses a corresponding address translation buffer to translate virtual addresses to real addresses.

Address translator and address translation method

It is determined whether an i-th instruction is for a memory access. If the i-th instruction is the memory access, it is determined whether an address to access according to the i-th instruction coincides with an address that has been accessed by a first execution block. If the addresses coincide with each other, it is determined whether a cycle of a second execution block currently executing precedes that of the first execution block. If the cycle of the second execution block precedes that of the first executing block, a memory model is accessed. A necessary number of cycles for execution of a j-th instruction is added to the current number of cycles, and the address, a cycle, data, and a data size at the time of the current access (before re-writing) are written in a delay table.

Cycle simulation method, cycle simulator, and computer product

Core model processing of a processor model PE1 and a processor model PE2 is serialized. Therefore, processing time for the inter-core-model communication is required between the core model processing of a first processor model and the core model processing of a second processor model. The inter-core-model communication processing is performed such that the inter-core-model communication required for the simulation processing of a multi-processor model is performed in parallel with the core model processing.

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Kawasaki, Japan

Atsushi Ike