Hitachi, Ltd.

Elpida Memory, Inc.

Micron Technology Incorporated

Ps4 Luxco S.a.r.l.

Hitachi Ulsi Engineering Corp.

Other

Longitude Semiconductor S.a.r.l.

Atsushi Hiraishi

Yutaka Kobayashi

Toshio Sugano

Shigeru Takahashi

Masahiro Iwamura

Tatsumi Yamauchi

Takashi Akioka

Yuji Yokoyama

Koichiro Ishibashi

Shuji Ikeda

Yoji Nishio

Toshiaki Yamanaka

Satoshi Meguro

Naotaka Hashimoto

Atsuyoshi Koike

Nobuyuki Moriwaki

Hideaki Uchida

Katsuro Sasaki

Seigou Yukutake

Shunichi Saito

Akira Ide

Soichiro Hashiba

Isamu Kuramoto

Atsuo Watanabe

Takahide Ikeda

Fumiyuki Osanai

Nobuyuki Gotou

Hideharu Yahata

Sadayuki Morita

Kenichi Fukui

Mitsuru Hirao

Masataka Minami

Osamu Saito

Takahiro Nagano

Katsumi Ogiue

Masahiro Yamaguchi

Masanori Odaka

Yoshiaki Yazawa

Akira Fukami

Shinji Nakazato

Nobuo Tamba

Takahiro Sonoda

Hiroshi Toyoshima

Masayuki Ohayashi

Nobuo Tanba

Kazunori Onozawa

Kunihiro Komiyaji

Tomohiro Nagano

Hirofumi Zushi

Haruko Kawachino

Masashige Harada

Nobuyuki Gotoo

Kouichirou Yamada

Tadashi Kuramoto

Nozomu Matsuzaki

Mitsuaki Katagiri

Tsutomu Hara

Yasuhiro Takai

Naohiro Momma

Masahiro Yamamura

Koichiro Aoki

Atsuo Koshizuka

Hiroki Fujisawa

Kazumasa Yanagisawa

Masayuki M Nakamura

Seiji Narui

Satoshi Isa

Hideyuki Aoki

Sadayuki Ohkuma

Satoshi Oguchi

Tsuyoshi Tomoyama

Masanori Shibamoto

Koichi Motohashi

Osamu Saitoo

Ryuichi Saitoo

Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes a signal receiver that receives information signal: a control circuit that provides a plurality of control signals; and a signal receiver replica circuit that receives a first reference signal. The signal receiver replica circuit includes a plurality of receivers. Each receiver of the plurality of receivers receives the first reference signal and a corresponding control signal of the plurality of control signals, and further provides an output signal.

Timing control for input receiver

Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes a signal receiver that receives information signal; a control circuit that provides a plurality of control signals; and a signal receiver replica circuit that receives a first reference signal. The signal receiver replica circuit includes a plurality of receivers. Each receiver of the plurality of receivers receives the first reference signal and a corresponding control signal of the plurality of control signals, and further provides an output signal.

Apparatuses are presented for a semiconductor device utilizing dual I/O line pairs. The apparatus includes a first I/O line pair coupled to a first local I/O line pair. A second I/O line pair may be provided coupled to a second local I/O line pair. The apparatus may further include a first bit line including at least a first memory cell and a second memory cell, and a second bit line including at least a third memory cell and a fourth memory cell may be provided. The first local I/O line pair may be coupled to at least one of the first and second bit lines, and the second local I/O line pair is coupled to at least one of the first and second bit lines.

Apparatuses and methods for a memory device with dual common data I/O lines

A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation.

Semiconductor device

Disclosed herein is a device that includes a silicon interposer having wiring lines on first and second wiring layers. The wiring lines includes first, second and third wiring lines provided on the first wiring layer and a fourth wiring line provided on the second wiring layer. The third wiring line is arranged between the first and second wiring lines on the first wiring layer. The fourth wiring line is overlapped with the third wiring line. Each of the first, second and fourth wiring lines conveys a power supply potential to first and second semiconductor chips mounted on the silicon interposer, and the third wiring line conveys a first signal communicated between the first and second semiconductor chips.

Semiconductor device having silicon interposer on which semiconductor chip is mounted

Disclosed herein is a memory module that includes a module substrate, data connectors, memory devices, and data register buffers. A first main surface of the module substrate has first and second memory mounting areas. One of the first and second main surfaces of the module substrate has a register mounting area located between the first and second memory mounting areas in a planner view. The memory devices include a plurality of first memory devices that are mounted on the first memory mounting area and a plurality of second memory devices that are mounted on the second memory mounting area. The data register buffers are mounted on the register mounting area. The data register buffers transfers write data supplied from the data connectors to the memory devices, and transfers read data supplied from the memory devices to the data connectors.

Memory module including plural memory devices and data register buffer

Disclosed herein is a device that includes: a data strobe terminal; a data terminal; a first output driver coupled to the data strobe terminal; a second output driver coupled to the data terminal; and a data control circuit configured to enable the first and second output drivers to function as termination resistors in different timings from each other.

Semiconductor device having ODT function

An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TLfrom the data transferring element to a first branch point Swhere a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TLfrom the first branch point Sto a second branch point Swhere a second branch line is branched. A wiring length TLfrom the second branch point Sto a third branch point Swhere a third branch line is branched is configured to become greater than the wiring lengths TLand TL

Apparatus having a wiring board and memory devices

A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.

Load reduced memory module and memory system including the same

A multi-layer printed circuit board for mounting memories, includes: laminated wiring layers on which wiring is arranged; and a plurality of interlayer connection components which electrically connect at least two of the wiring layers. At least one of the plurality of interlayer connection components is a blind via-hole.

Multi-layer printed wiring board

Address line wiring structure and printed wiring board having same

In a multi-rank memory module having a terminal resistance of a data input/output padand a terminal resistance control padthat inputs a signal that controls on/off of the terminal resistance, a high-speed operation is enabled with the aid of an enclosed terminal resistance, even in cases where the number of ranks is greater than that of terminal resistance control terminals (ODT terminals) provided on the memory module. To this end, a terminal resistance control padof a memory chip, having a longer length of an interconnect between a data buson a module substrateand a data input/output pad, is connected to a terminal resistance control interconnectorto control the on/off of the terminal resistance from the ODT terminal. A terminal resistance control pad on a memory chip, having a shorter length of an interconnect between the data buson the module substrate and the data input/output pad, is connected to a fixed potentialto turn on the terminal resistance.

Memory module, method for using same and memory system

Growing community of inventors

Tokyo, Japan

Atsushi Hiraishi