Sony Corporation

Nippon Telegraph and Telephone Corporation

Atsushi Hirabayashi

Kenji Komori

Kosuke Fujita

Norihiro Murayama

Kyoichi Murakami

Masaaki Ishihara

Atsushi Takada

Kosuke Sakata

Yoshito Kogure

Service failure information can be quickly and accurately disseminated to appropriate targets. A service failure information dissemination systemreceives alarm information notifying that a failure has occurred in a service or a device for providing a service and related information that relates to the alarm information, obtains the degree of influence of the failure for each service type based on the alarm information and the related information, determines a dissemination target and a dissemination means of failure information based on the degree of influence, creates failure information according to the dissemination means, and disseminates the failure information to the dissemination target through the dissemination means.

Failure information announcement device and failure information announcement method

Provided are an apparatus failure influence range recognition apparatus, an apparatus failure influence range recognition method, and a program capable of billing for a proper call charge for a call suspected of non-provision of a service. An apparatus failure influence range recognition apparatus includes a reception unit configured to receive apparatus failure information which is failure information of an element constituting a network, user information which is information regarding a user of a service, and call details information of an IP telephone, and a calculation unit configured to calculate, by linking the apparatus failure information, the user information, and the call details information with each other, a subtracted call charge with respect to a call charge for a suspected call influenced by an apparatus failure.

Device failure influence range grasping apparatus, device failure influence range grasping method, and program

An amplifier circuit including a plurality of CMOS (Complementary Metal Oxide Semiconductor) inverter circuits connected in parallel with each other. The CMOS inverter circuits each include a first PMOS (P-channel Metal Oxide Semiconductor) transistor, a first NMOS (N-channel Metal Oxide Semiconductor) transistor, gates of the first PMOS and NMOS transistors, a second PMOS transistor, a first switch connected to a gate of the second PMOS transistor, a second NMOS transistor, and a second switch connected to a gate of the second NMOS transistor.

Amplifier circuit, semiconductor device, and controlling method

Disclosed herein is a subtractor circuit for outputting an output voltage as a difference between a first input voltage and a second input voltage. The subtractor circuit may include a first semiconductor element, a second semiconductor element, a third semiconductor element, a fourth semiconductor element, a fifth semiconductor element, and a sixth semiconductor element configured to each invert a voltage input to an input terminal and output the inverted voltage from an output terminal; an input terminal of the first semiconductor element; an input terminal of the second semiconductor element; an output terminal of the first semiconductor element; and an output terminal of the third semiconductor element.

Subtractor circuit and operational amplifier

A signal amplifier includes a discrete-variable-gain amplifying unit, a gain of which takes a discrete value and changes stepwise, a linear-variable-gain amplifying unit connected in series to the discrete-variable-gain amplifying unit, a gain of which changes continuously, control-signal outputting means for detecting a level of an output signal from a series connection circuit of the discrete-variable-gain amplifying unit and the linear-variable-gain amplifying unit and outputting a control signal corresponding to a difference between the level of the output signal and a reference voltage set as a comparative level to control the gain of the linear-variable-gain amplifying unit, and gain-switching control means for controlling to switch the gain of the discrete-variable-gain amplifying unit when the control signal deviates from a setting range for the control signal that is set according to a variable gain range of the discrete-variable-gain amplifying unit.

Signal amplifier

An impedance conversion circuit including: a first voltage-to-current converter and a second voltage-to-current converter supplied with differential input signal voltages; an inverting amplifier; and a third voltage-to-current converter for feedback; wherein a first resistance and a second resistance are connected in series with each other between an input terminal and an output terminal of the inverting amplifier, an output terminal of the first voltage-to-current converter is connected to the input terminal of the inverting amplifier, an output terminal of the second voltage-to-current converter is connected to a connection node of the first resistance and the second resistance, the output terminal of the inverting amplifier is connected to an input terminal of the third voltage-to-current converter, an output terminal of the third voltage-to-current converter is connected to an input terminal of the first voltage-to-current converter, and an impedance is connected between the connection node and a ground.

Impedance conversion circuit and integrated circuit including thereof

A conventional multiplier which uses a MOS transistor has a subject that, in order to compensate for a variation of a bias voltage or the like, it is necessary to add a complicated correcting circuit to an outputting section or the like, and the circuit scale becomes great and the power consumption increases. A multiplier includes NMOS transistors () and constant voltage sources () connected to the gates of the NMOS transistors (), respectively, and the voltage value of a constant voltage source () and the voltage value of another constant voltage source () are set equal to each other. Further, the NMOS transistor () and the NMOS transistor () are formed same as each other.

Multiplier

An amplifier circuit includes a CMOS inverter circuit that eliminates a DC offset caused by variations in characteristics of elements in each manufacturing process and is thus applicable to analog signal processing. The CMOS inverter circuit includes a PMOS transistor, a first NMOS transistor, a second NMOS transistor connected to the first NMOS transistor to increase a source voltage of the first NMOS transistor, and DC offset detecting means for detecting a DC offset and for applying a voltage adjusted so as to reduce the DC offset to a gate of the second NMOS transistor.

Amplifier circuit

A voltage/current converter circuit includes a first differential pair circuit containing a first pair of MOS transistors, a second differential pair circuit containing a second pair of MOS transistors wherein the drain terminals thereof are connected to each of the source terminals of the first MOS transistor differential pair circuit, and a resistor element connected between the sources of the second MOS transistor differential pair circuit, wherein the gates of the second pair of MOS transistors are mutually connected to the drains of the MOS transistors of the other side, and the sources of the two MOS transistors are each grounded via an electric current source. Thus, a high-gain amplifier with improved linearity is realized with a small number of elements, thereby reducing electric power consumption and reduced IC chip surface area.

Voltage/current converter circuit and high-gain amplifying circuit

A high impedance circuit capable of operating at a low voltage without narrowing the dynamic range is provided, which includes a first and a second transistors forming differential-pair type circuit, a third and fourth transistors, a pair of collector resistance elements, a resistance element and a pair of current source circuits. The third and the fourth transistors serve as emitter follower circuits which also functions as a DC shift with respect to the differential-pair type circuit, as well as buffer circuits for heightening an input impedance of the first and the second transistors looked from the base side of the third and the fourth transistors. The current flowing in the resistance element is made current-fedback with respect to the resistance elements by the third and the fourth transistors. The input impedance is determined as Z,&equals;V,/ i,&equals;(R,&times;R,)/(R,&minus;R,), and when R,&equals;R,, the high impedance circuit becomes infinite impedance.

High impedance circuit

A high impedance circuit capable of operating at a low voltage without narrowing the dynamic range is provided, which includes a first and a second transistors forming differential-pair type circuit, a third and fourth transistors, a pair of collector resistance elements, a resistance element and a pair of current source circuits. The third and the fourth transistors serve as emitter follower circuits which also functions as a DC shift with respect to the differential-pair type circuit, as well as buffer circuits for heightening an input impedance of the first and the second transistors looked from the base side of the third and the fourth transistors. The current flowing in the resistance element is made current-fedback with respect to the resistance elements by the third and the fourth transistors. The input impedance is determined as Z1=V1/i3=(R1.times.R2)/(R1-R2), and when R1=R2, the high impedance circuit becomes infinite impedance.

An impedance conversion circuit for the use with a video apparatus, an audio apparatus, or a communication apparatus is provided. The impedance conversion circuit can be used at a frequency higher than that conventionally used and is suitable for formation as an integrated circuit. A video apparatus using this impedance conversion circuit, and the like are also proposed. Driving current is supplied to first and second terminals of an impedance circuit in accordance with voltages of first and second input terminals, respectively, and current is made to flow out of the second and first output terminals in accordance with the first and second terminal voltages of the impedance circuit, respectively.

Impedance conversion circuit, video apparatus, audio apparatus, and

An amplifier circuit in which a differential pair of transistors (1a), (1b) is provided. An impedance (2) of a value 2.Z.sub.e is connected in series between the emitters of the transistors (1a), (1b) and these emitters are grounded by way of current sources (3a), (3b) respectively. Input signal sources (4a), (4b) of voltage values.+-.V.sub.IN are connected to the bases of the transistors (1a), (1b) by way of the base-emitter paths of the transistors (5a), (5b) which form a buffer circuit (10). The emitters of the transistors (5a), (5b) are in turn grounded by way of current sources (6a), (6b) respectively. Further, the collectors of each of the transistors (1a), (1b) are connected to the base of the other transistors by way of the base-emitter paths of the transistors (5a), (5b) respectively.

Negative amplifier circuit

A two-terminal paired circuit is disclosed which comprises two sets of differential pairs wherein a first set of the differential pair includes two transistors collectors of which are connected to a pair of input terminals and to a bias circuit serving also as a DC shift, bases of which are connected to the bias circuit to apply a voltage feedback from the collectors to the bases and emitters of which are connected to a constant current source and have an impedance element connected therebetween, a second set of the differential pair includes two transistors collectors of which are connected to a pair of output terminals and to a bias circuit serving also as a DC shift, bases of which are connected to the bias circuit to apply a voltage feedback from the collectors to the bases and emitters of which are connected to a constant current source and have an impedance element connected therebetween, and the voltage feedbacks together with the two sets of differential pairs are applied symmetrical with respect to left and right, whereby the impedances connected between the emitters exist in series between the input and output terminals.

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Tokyo, Japan

Atsushi Hirabayashi