Sony Corporation

Atsushi Hasebe

Norikazu Ito

Satoshi Yoneya

Ryohei Kato

Masahiro Kato

Atsushi Kikuchi

Hiroyuki Fujita

Yasumasa Kodama

Satoshi Yutani

Norio Ebihara

Taro Shigata

Ryouhei Kato

A matrix switcher selectively seizes plural compressed pictures and converts P-frames in a GOP into I-frames while modifying prediction data of B-frames in the GOP. A decoder expands the compressed pictures into original pictures. An input buffer memory converts the picture signals into component signals while converting the transfer rate. A picture processing unit performs various picture signal processing operations on the picture signals. An encoder encodes the processed picture signals for compression. An output buffer memory converts the transfer rate of sent-out data which are compressed processed signals. A controller controls processing operations by the matrix switcher, decoder, input buffer memory, picture processing unit, encoder and the output buffer memory. The compressed pictures processed by inter-frame compression can be switched smoothly. Moreover, picture processing can be performed on a wide gamut of pictures from still pictures to moving pictures, free-format pictures, pictures not dependent on transfer rate and on scalable-format pictures.

Picture signal processing apparatus

An information signal transmission device in which information signals are transmitted to requesting parties responsive to requests made by plural requesting parties. The signals of the leading end of the information signals are pre-stored in a versing-up memory and, when a request is made by a requesting party, an output signal of a buffer memory unit for time axis expansion is transmitted to such requesting party after an output signal of the versing-up memory unit is transmitted to such requesting party.

Apparatus for supplying a leading-end signal from leading-end memory

In processing image data by a plurality of processors in accordance with processing information from a host computer, such processing information is stored in a program memory at an address indicated by the host computer and is read from the program memory and supplied to the processors. The processing information stored in the program memory is held therein until new processing information is supplied by the host computer and, in response to a read signal from the host computer, the processing information stored at a respective address in the program memory is supplied therefrom to the host computer which can confirm whether such information has been correctly transmitted to the processors.

Image processing system having plurality of processors acting on image

An information processing system including an input/output section, a memory section, and a data processing section for communicating data via the memory section in block units between the input/output section and the data processing section to effect a processing characterized in that a signal indicating an end of the processing in block units is supplied from the data processing section to the input/output section and that a processing start timing signal formed depending on the signal indicating the processing end delivered from the output section is delivered to the data processing section, the processing start timing signal being synchronized with a data block period.

System for asynchronously generating data block processing start signal

An apparatus for to extracting a video signal corresponding to a moving object in a video signal representing moving and stationary object comprises means for detecting a contour in the video signal and storing the contour data of successive frame in two frame buffers. Contour data stored in the two frame buffers are compared with each other so that a transition between corresponding portions of the two frame buffers are detected. This transition image is also stored in another memory and additional pixel transitions are interpolated at pixels having adjacent transitions. Thereafter, an area encompassed by the pixels representing the transition is combined with the video signal so that a motion video signal can be extracted.

Apparatus for detecting a moving object in a motion picture sequence

An information processing apparatus comprising a program supplying portion, write signal generator, and a data processor, which includes a microprogram controller, microprogram memory, arithmetic unit, and a selector for selecting in an alternative way an address from the microprogram controller and an address from the program supplying portion and supplying the same to the microprogram memory. In the apparatus, it is adapted such that, in a first (program execution) mode, the address from the microprogram controller is supplied through the selector to the microprogram memory, in a second (reset, or stop) mode, the microprogram controller is supplied with a signal, whereby the same is caused to continuously generate program start addresses, and in a third (program transfer) mode, the address from the program supplying portion is supplied through the selector means to the microprogram memory and, according to a write signal from the write signal generator, the program from the program supplying portion is written in the microprogram memory. When supplying a plurality of different programs from the program supplying portion to the processors operating under the program, such a method can be used to treat the whole of the plurality of different programs as one program and supply this program to the processors at one time of transfer and separately supply an execution start address of one program out of the plurality of different programs to each of said processors.

Multiple mode microprogram controller

In a high-speed arithmetic processor, a first number that has an absolute value that can exceed one is multiplied by a second number that has an absolute value not exceeding one. If the first number exceeds one it is divided into an integer and a part having a value less than one. The second number is accumulated as an addend a number of times equal to the integer to produce a sum. The second number and the part of the first number having a value less than one are supplied to a multiplier to produce a partial product. An adder adds the partial product to the sum, thereby obtaining a final product of the first and second numbers. The multiplication is thereby performed in a number of steps which is minimized and never varies, regardless of whether the absolute value of the first number is, for example, less than one, at least one but less than two, or at least two but less than three. This speeds up the arithmetic processing and simplifies the programming therefor.

Growing community of inventors

Kanagawa, Japan

Atsushi Hasebe