Fujitsu Corporation

Fujitsu Microcomputer Systems Limited

Atsushi Fujihira

Takayoshi Taniai

Yuji Shibata

Taizo Sato

Takeshi Kitahara

Tadashi Saitoh

Hiroya Kawasaki

Masaki Kira

Masato Mitsuhashi

Hidetoshi Iwasa

Kiyofumi Mitsuze

Harunobu Ogawa

A switching system for controlling internal apparatuses provided within an exchange system includes a central controller and a switching module including a plurality of objective apparatuses, each objective apparatus including a control data end unit, controlled by the central controller based on DMA communication and SD/SCN signal. Further, the central controller includes a first processor access controller which transfers control data to the control data end unit, in order to check and control each of objective apparatus, based on the DMA communication and the SD/SCN signal. The switching module includes a second processor access controller which relays the control data transferred between the first processor access controller and a plurality of control data end units-based on the DMA communication and the SD/SCN signal. According to the present invention, it is possible to realize high speed data transfer and high reliability based on the DMA communication and the SD/SCN signal between the central controller and each objective apparatus.

Switching system for controlling internal apparatuses in an exchange system

A cache memory, and a data processor including the cache memory, for processing at least one variable length instruction from a memory and outputting processed information to a control unit, such as a central processing unit (CPU). The cache memory includes a unit for decoding an instruction length of a variable length instruction from the memory, and a unit for storing the variable length instruction from the memory, together with the decoded instruction length information. The variable length instruction and the instruction length information thereof are fed to the control unit. Accordingly, the cache memory enables the control unit to simultaneously decode a plurality of variable length instructions and thus realize high speed processing.

Cache memory and data processor including instruction length decoding

A fetching operation break unit breaks a fetching operation of a block data from a main memory, when a system bus is released during the fetching of the block data and also when data written due to a write access by an external device into the main memory coincides with the fetching of one block data. Further, a notification means notifies the state of the fetching operation to an external cache memory. Therefore, the external cache memory can confirm whether a block-in operation of the microprocessor is broken or not, and the contents of the external cache can correctly coincide with the contents of the internal cache and the main memory by carrying out a steal operation, so that the operational reliability of a computer system can be increased.

Data processing device for maintaining coherency of data stored in main

A direct memory access controller adaptable to control a direct memory access transfer in a data processing system which includes at least a central processing unit and a system bus, comprises a register coupled to the system bus for outputting a transfer terminate request signal which instructs a normal termination when the central processing unit is operating and a write operation is carried out with respect to the register from the central processing unit, and a transfer termination part coupled to the register for stopping to accept a new transfer request signal or stopping to generate a transfer request signal responsive to the transfer termination request signal so as to make an instructed channel inactive.

Direct memory access controller

A direct memory access controller coupled to a system bus of a system including a memory, for controlling a data transfer by a direct memory access, includes a register registering a code which designates one of a plurality of descriptor formats, each of which defines both the number and type of descriptors necessary for the data transfer by the direct memory access, a group of registers for registering descriptors defined in one of the descriptor formats which is selected by the code registered in the register, a controller for controlling the data transfer by the direct memory access in accordance with the descriptors defined in the selected one of the descriptor formats registered in the register.

A data transfer controlling apparatus for direct memory access comprising one or more first microaddress registers, each of which registers stores microaddress information for program processing of the data transfer for a corresponding channel; a second microaddress register which stores microaddress information for program processing other than the program processing of the data transfer; a micro read only memory operatively connected to said first and second microaddress registers, for storing microinstructions and outputting a predetermined microinstruction in accordance with microaddress information read out from a selected one of the first microaddress registers and the second microaddress register; and an incremental element operatively connected to said first and second microaddress registers, for incrementing the value of the microaddress information read out from the selected one of the first microaddress registers and the second microaddress register, and for writing the incremented microaddress information to the selected one of the first microaddress registers and the second microaddress register; the microaddress information stored in one of the first microaddress registers for the corresponding channel being read out when program processing of data transfer for the corresponding channel is carried out, the microaddress information stored in the second microaddress register being read out when program processing other than the program processing of data transfer is carried out.

Data transfer controlling apparatus for direct memory access

A line condition data collecting system for a telephone exchange includes an image memory in a central processing unit which stores line condition data to reduce the amount of time the central controller in the central processing unit waits for the line condition data. A signal receiving memory in the telephone exchange stores the line condition data and is sequentially accessed by an image memory controller autonomously from the central controller in the central processing unit. When the central controller requires line condition data, the image memory is checked and if the line condition data stored therein is valid, it is supplied to the central controller. If the line condition data in the image memory is invalid, a conventional access request is made to the signal receiving memory, but this occurs less frequently than in a conventional system.

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Kawasaki, Japan

Atsushi Fujihira