Renesas Electronics Corporation

Renesas Technology Corp.

Mitsubishi Denki Kabushiki Kaisha

Atsushi Amo

Shunji Kubo

Atsushi Hachisuka

Tatsuo Kasaoka

Masatoshi Kimura

Tohru Kawai

Kaoru Motonami

Eiji Tsukuda

Hiroaki Sekikawa

A semiconductor device is provided with an SOI substrate which includes a semiconductor substrate, a ferroelectric layer and a semiconductor layer, and has a first region in which a first MISFET is formed. The first MISFET includes: the semiconductor substrate in the first region; the ferroelectric layer in the first region; the semiconductor layer in the first region; a first gate insulating film formed on the semiconductor layer in the first region; a first gate electrode formed on the first gate insulating film; a first source region located on one side of the first gate electrode and formed in the semiconductor layer in the first region; and a first drain region located on the other side of the first gate electrode and formed in the semiconductor layer in the first region.

Semiconductor device

A trench is formed by removing a portion of each of the charge accumulation film and the insulating film located between the control gate electrode and the memory gate electrode. The insulating film is formed in the trench so that the upper surface of each of the insulating film and the charge accumulation film is covered with the insulating film. When exposing the upper surface of the control gate electrode and the memory gate electrode, the upper surface of each of the insulating film and the charge accumulation film is not exposed.

Method of manufacturing semiconductor device having split-gate memory and MISFET

A semiconductor device according to one embodiment includes: a semiconductor substrate having a first surface; a first conductive film that is located over the first surface and is formed to circle in plan view; a second conductive film that is located over the first surface and surrounds the outer periphery of the first conductive film in plan view; a first insulating spacer located between the first conductive film and the second conductive film; a first gate insulating film that is located between the first surface and the first conductive film and the accumulated amount of charges of which changes due to a change in the voltage between the first conductive film and the semiconductor substrate; and a second gate insulating film located between the first surface and the second conductive film.

Semiconductor device and manufacturing method of semiconductor device

An object is to provide a reliability-improved semiconductor device having a MONOS memory that rewrites data by injecting carriers into a charge storage portion. When a memory gate electrode having a small gate length is formed in order to overlap a carrier injection position in write operation with that in erase operation, each into an ONO film including a charge storage portion, the ONO film is formed in a recess of a main surface of a semiconductor substrate for securing a large channel length. In a step of manufacturing this structure, control gate electrodes are formed by stepwise processing of a polysilicon film by first and second etching and then, the recess is formed in the main surface of the semiconductor substrate on one side of the control gate electrode by second etching.

Semiconductor device and method of manufacturing same

In a semiconductor device including a split gate type MONOS memory, and a trench capacitor element having an upper electrode partially embedded in trenches formed in the main surface of a semiconductor substrate, merged therein, the flatness of the top surface of the upper electrode embedded in the trench is improved. The polysilicon film formed over the semiconductor substrate to form a control gate electrode forming a memory cell of the MONOS memory is embedded in the trenches formed in the main surface of the semiconductor substrate in a capacitor element formation region, thereby to form the upper electrode including the polysilicon film in the trenches.

Semiconductor device and a manufacturing method thereof

A method of manufacturing a semiconductor device includes providing a semiconductor substrate including a main surface, the main surface including a first area and a second area, which is different from the first area in a plan view, forming a first trench in the main surface of the semiconductor substrate in the first area, after the forming the first trench, forming a first insulating film on a side wall surface and a bottom face of the first trench, and after the forming the first insulating film, forming a first conductor film over the semiconductor substrate in the first area and a second area to embed a portion of the first conductor film into the first trench through the first insulating film.

Method for manufacturing semiconductor device including patterning conductor film disposed on insulating film

To reduce a manufacturing cost of a semiconductor device in which a high breakdown voltage transistor and a trench capacitive element in which a part of an upper electrode is embedded in a trench formed in a main surface of a semiconductor substrate are mixed together. After an insulating film is formed over a main surface of a semiconductor substrate so as to cover a trench formed in the main surface of the semiconductor substrate, the insulating film is processed to form an upper electrode of a capacitive element, a gate insulating film which insulates the semiconductor substrate to be a lower electrode, and a gate insulting film of a high breakdown voltage transistor.

Method for manufacturing semiconductor device including memory cell of nonvolatile memory, capacitance element, and transistors

A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (), an insulating layer () on the semiconductor substrate (), a plurality of contact plugs () in the insulating layer (), and an insulating layer () where capacitors (), a plurality of contact plugs (), barrier metal layers () and copper interconnections () are formed. Source/drain regions () in the upper surface of the semiconductor substrate () are electrically connected to the copper interconnections (). One of adjacent source/drain regions () in the upper surface of the semiconductor substrate () is electrically connected to the copper interconnection (), while the other is electrically connected to the capacitor ().

In order to improve the discharging speed of potential from a match line, a semiconductor device includes a capacitor, a memory transistor having a source/drain region connected to a storage node of the capacitor, a search transistor having a gate electrode connected to the storage node, and a stacked contact connecting a match line and the source/drain region of the search transistor. The storage node has a configuration in which a sidewall of the storage node facing the match line partially recedes away from the stacked contact such that a portion of the sidewall in front of the stacked contact in plan view along the direction of the match line is located farther away from the stacked contact than the remaining portion of the sidewall.

Growing community of inventors

Tokyo, Japan

Atsushi Amo